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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

312

Inbound PCIe access is performed on the VCore Shared Bus (SBA) in the same way as ordinary VCore-

III CPU access. By means of the switch core Access block it is possible to access the Switch Core

Controller.

The SI, MIIM, and VRAP interfaces attach directly to the CSR. Through the VCore SBA access block, it is

possible to access the VCore shared bus. For more information, see Access to the VCore Shared Bus.

The external CPU can coexist with the internal VCore-III CPU, and hardware-semaphores and interrupts

are implemented for inter-CPU communication. For more information, see Mailbox and Semaphores.

4.5.1

There are three different groups of registers in the device:

•

Switch Core

•

Fast Switch Core

•VCore

The Switch Core registers and Fast Switch Core registers are separated into individual register targets

and attached to the Switch Core Register bus (CSR). The Fast Switch Core registers are placed in the

DEVCPU_QS and DEVCPU_ORG register targets. Access to Fast Switch Core registers is less than

0.1 µs; other Switch Core registers take no more than 1 µs to access.

The VCore registers are attached directly to the VCore shared bus. The access time to VCore registers is

negligible (a few clock cycles).

Although multiple masters can access VCore registers and Switch Core registers in parallel without

noticeable penalty to the access time, the following exceptions apply.

•

When accessing the same Switch Core register target (for example, DEVCPU_GCB), the second

master to attempt access has to wait for the first master to finish (round robin arbitration applies.)

This does not apply to Fast Switch Core register targets (DEVCPU_QS and DEVCPU_ORG).

•

If both the VCore-III CPU and the PCIe master are performing Switch Core Register bus (CSR)

access, both need to be routed through the Switch Core Access block. The second master has to

wait for the first master to finish (shared bus arbitration applies).

•

If two or more SI, MIIM, or VRAP masters are performing VCore register access, they all need to go

through the VCore SBA Access block. Ownership has to be resolved by use of software (for

example, by using the build-in semaphores).

The most common multimaster scenario is with an active VCore-III CPU and an external CPU using

either SI or VRAP. In this case, Switch Core register access to targets that are used by both CPUs may

see two times the access time (no more than 2 µs).

4.5.2

Serial Interface in Slave Mode

This section provides information about the function of the serial interface in slave mode.

The following table lists the registers associated with SI slave mode.

The serial interface implements a SPI-compatible protocol that allows an external CPU to perform read

and write access to register targets within the device. Endianess and bit order is configurable, and

several options for high frequencies are supported.

The serial interface is available to an external CPU when the VCore-III CPU does not use the SI for Flash

or external SI access. For more information, VCore-III System and CPU interfaces.

Figure 102 •

SI Slave Mode Register

Description

DEVCPU_ORG::IF_CTRL

Configuration of endianess and bit order

DEVCPU_ORG::IF_CFGSTAT

Configuration of padding

ICPU_CFG::GENERAL_CTRL

SI interface ownership

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