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VSC7440 Datasheet(PDF) 325 Page - Microsemi Corporation |
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VSC7440 Datasheet(HTML) 325 Page - Microsemi Corporation |
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325 / 444 page  VCore-III System and CPU Interfaces VMDS-10492 VSC7440 Datasheet Revision 4.2 308 Figure 100 • Shared Bus Memory Map Note: When the VCore-III system is protected from a soft reset using ICPU_CFG::RESET.CORE_RST_CPU_ONLY, a soft reset does not change shared bus memory mapping. For more information about protecting the VCore-III system when using a soft reset, see Clocking and Reset, page 306. If the boot process copies the SI Flash image to DDR3/DDR3L, and if the contents of the SI memory and the DDR3 memory are the same, software can execute from the mirrored region when swapping from boot mode to normal mode. Otherwise, software must be execute from the fixed SI Flash region when changing from boot mode to normal mode. The Frame DMA has dedicated access to PCIe outbound and to the DDR3/DDR3L. This means that access on the SBA to other parts of the device, such as register access, does not affect Frame DMA injection/extraction performance. Reserved PCIe DMA Reserved Reserved DDR3/DDR3L Mirror of SI Flash Chip Registers 0x00000000 0x80000000 0x20000000 0xFFFFFFFF Boot Mode (Physical), 512 MB 0x10000000 256 MB 1 GB 512 MB Mirror of DDR3/DDR3L Chip Registers 0x00000000 0x80000000 0x20000000 0xFFFFFFFF Normal Mode (Physical), 512 MB Reserved 512 MB 1 GB 256 MB 0x70000000 0x70000000 256 MB SI Flash 0x40000000 256 MB DDR3/DDR3L 512 MB 0x40000000 Reserved 0x50000000 256 MB 512 MB SI Flash 0x50000000 256 MB 512 MB Reserved DDR3/DDR3L Chip Registers 0x00000000 0x80000000 0xFFFFFFFF Boot Mode (Physical), 1 GB(1) 0x10000000 PCIe DMA 1 GB Mirror of DDR3/DDR3L Chip Registers 0x00000000 0x80000000 0xFFFFFFFF Normal Mode (Physical), 1 GB(1) DDR3/DDR3L 1 GB 1 GB 256 MB 0x70000000 0x70000000 256 MB SI Flash 0x40000000 0x40000000 Reserved 1 GB 0x50000000 256 MB 512 MB SI Flash 0x50000000 256 MB 512 MB 1 GB 0xC0000000 0xC0000000 Reserved Mirror of SI Flash 256 MB 768 MB PCIe DMA 1 GB PCIe DMA 1 GB 0xC0000000 0xC0000000 1. To enable support 1 gigabyte (GB) of DDR3/DDR3L memory (and the associated memory map), set ICPU_CFG::MEMCTRL_CFG.DDR_512MBYTE_PLUS. |
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