VSC7440 datasheet(321/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

304

VCORE_CFG[3:0]

Configuration of VCore system startup conditions.

0000: VCore-III CPU is enabled (Little Endian mode) and boots from SI (the SI slave is

disabled).

0001: PCIe 1.x endpoint is enabled. Port 10 is enabled for SFI 10G, and NPI port 4 is enabled

for SERDES NoAneg 1G FDX NoFC. VRAP block is accessible through the NPI port.

Automatic boot of VCore-III CPU is disabled, and SI slave is enabled.

0010: PCIe 1.x endpoint is enabled. Port 6 is enabled for SERDES NoAneg 1G FDX NoFC,

and NPI port 4 is enabled for SERDES NoAneg 1G FDX NoFC. VRAP block is accessible

through the NPI port. Au-tomatic boot of VCore-III CPU is disabled, and SI slave is enabled.

0011: PCIe 1.x endpoint is enabled. Port 0 is enabled for SERDES NoAneg 1G FDX NoFC,

and NPI port 4 is enabled for SERDES NoAneg 1G FDX NoFC. VRAP block is accessible

through the NPI port. Au-tomatic boot of VCore-III CPU is disabled, and SI slave is enabled.

0100: PCIe 1.x endpoint is enabled. Port 10 is enabled for SFI 10G, and NPI port 9 is enabled

for SFI 10G. VRAP block is accessible through the NPI port. Automatic boot of VCore-III CPU

is disabled, and SI slave is enabled.

0101: PCIe 1.x endpoint is enabled. NPI port 9 is enabled for SFI 10G. VRAP block is

accessible through the NPI port. Automatic boot of VCore-III CPU is disabled, and SI slave is

enabled.

1000: PCIe 1.x endpoint is enabled. NPI port 4 is enabled for SERDES NoAneg 1G FDX

NoFC. VRAP block is accessible through the NPI port. Automatic boot of VCore-III CPU is

disabled, and SI slave is enabled.

1001: PCIe 1.x endpoint is enabled. Automatic boot of VCore-III CPU is disabled, and SI

slave is enabled.

1010: MIIM slave is enabled with MIIM address 0 (MIIM slave pins are overlaid on GPIOs).

Automatic boot of VCore-III CPU is disabled, and SI slave is enabled.

1011: MIIM slave is enabled with MIIM address 31 (MIIM slave pins are overlaid on GPIOs).

Automatic boot of VCore-III CPU is disabled, and SI slave is enabled.

1100: VCore-III CPU is enabled (Big Endian mode) and boots from SI (the SI slave is

disabled).

1111: Automatic boot of VCore-III CPU is disabled, and SI slave is enabled.

Other values are reserved and must not be used.

Table 228 •

Strapping (continued)

Description

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