VSC7440 datasheet(320/444 Pages) MICROSEMI

320 / 444 page

Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

303

For information about protecting the VCore CPU system during a soft-reset, see Clocking and Reset,

page 302.

3.36.1

Pin Strapping

Configure PLL2 reference clocks and VCore startup mode using the strapping pins on the GPIO

interface. The device latches strapping pins and keeps their value when nRESET to the device is

released. After reset is released, the strapping pins are used for other functions. For more information

about which GPIO pins are used for strapping, see GPIO Overlaid Functions, page 352.

By using resistors to pull the GPIOs either low or high, software can use these GPIO pins for other

functions after reset has been released.

Undefined configurations are reserved and cannot be used. VCore-III configurations that enable a front

port or the PCIe endpoint drive VCore_CFG[3:2] high when the front port or PCIe endpoint is ready to

use.

Table 228 •

Strapping

Description

REFCLK2_SEL

Strap high to enable PLL2.

0: PLL is source of switch core and VCore clocks. PLL2 is powered down, but can be enabled

through registers.

1: PLL2 is source of switch core and VCore clocks.

REFCLK_CONF[2:0]

Reference clock frequency for PLL.

REFCLK2_CONF[2:0] Configuration of reference clock frequency for PLL2, this is don't care if PLL2 is not enabled.

000: 125 MHz

001: 156.25 MHz

010: 250 MHz

100: 25 MHz

Other values are reserved and must not be used.

VSC7440 Datasheet(PDF) 320 Page - Microsemi Corporation