VSC7440 datasheet(319/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

302

DSM::TAXI_CAL_CFG[2].CAL_PGM_ENA = 1

Configure VCore to operate with lower frequency:

DEVCPU_PTP::PTP_SYS_CLK_CFG.PTP_SYS_CLK_PER_NS = 19,

DEVCPU_PTP::PTP_SYS_CLK_CFG.PTP_SYS_CLK_PER_PS100 = 192,

DEVCPU_GCB::SIO_CLOCK.SYS_CLK_PERIOD = 192,

DEVCPU_GCB::FAN_CFG.CLK_PERIOD = 192.

Configure assembler to operate with lower frequency:

ASM::TIME_TICK_CFG.TIME_TICK_VAL =

873812, ASM::PFC_TIMER_MAX.PFC_TIMER_MAX[1] = 3,

ASM::PFC_TIMER_MAX.PFC_TIMER_MAX[2] = 11,

ASM::PFC_TIMER_MAX.PFC_TIMER_MAX[3] = 27,

ASM::PFC_TIMER_MAX.PFC_TIMER_MAX[4] = 267,

ASM::PFC_TIMER_MAX.PFC_TIMER_MAX[5] = 2667.

Configure analyzer to operate with lower frequency:

ANA_AC_POL:COMMON_SDLB:DLB_CTRL.CLK_PERIOD_01NS = 192,

ANA_AC_POL:COMMON_BDLB:DLB_CTRL.CLK_PERIOD_01NS = 192,

ANA_AC_POL:COMMON_BUM_SLB:DLB_CTRL.CLK_PERIOD_01NS = 192,

LRN::AUTOAGE_CFG_1.CLK_PERIOD_01NS = 192.

Configure scheduler to operate with lower frequency:

HSCH::SYS_CLK_PER.SYS_CLK_PER_100PS = 192.

3.35.2

General Considerations in Low Power Mode

In low power mode, the switch core clock period is 19.2 ns. This must be taken into account for registers

where values depend on the switch core clock frequency. The following registers require special

attention:

•

AFI:TTI_TICKS:TTI_TICK_BASE.BASE_LEN

•

ANA_AC_POL::POL_UPD_INT_CFG.POL_UPD_INT

When the on-chip temperature sensor is enabled in low power mode, the time between temperature

sample refreshes (through HSIO::TEMP_SENSOR_STAT) is increased from 500 ìs to 1.5 ms.

The 1588 timing is less precise in low-power mode because the resolution of the timestamps changes

together with the core clock frequency.

During low power mode, SGMII/SERDES front ports operating in half-duplex mode cannot sustain the

minimum interframe gap of 12 bytes. The expected interframe gap is in the range of 14 to 15 bytes.

3.36

Clocking and Reset

There are two PLLs on the device: PLL and PLL2. The SERDES1G and SERDES6G reference clocks

are driven by PLL. The SERDES10G reference clocks are driven by PLL2. The switch-core clock and the

VCore System clocks are driven by either PLL or PLL2.

PLL2 is disabled by default, but it can be enabled in two ways. It can be strapped to enabled by pulling

strapping input REFCLK2_SEL high during device reset or it can be enabled after booting by writing

HSIO::CLK_CFG.PLL2_ENA.

When PLL2 is enabled during reset, by strapping REFCLK2_SEL high, then PLL2 drives the switch-core

and VCore System clocks. Otherwise, these clocks are driven by PLL. It is possible to re-configure the

source of the switch core clock (including the IEEE 1588 one-second timers) by using

HSIO::CLK_CFG.SWC_CLK_SRC. The VCore System clock source is not reconfigurable.

By using PLL2, the IEEE 1588 clock can be made independent of a clock recovered by Synchronous

Ethernet clock.

The reference clocks for PLL and PLL2 (REFCLK_P/N and REFCLK2_P/N) are either differential or

single-ended. The frequency can be 25 MHz (REFCLK_P/N only), 125 MHz, 156.25 MHz, or 250 MHz.

PLL and PLL2 must be configured for the appropriate clock frequency by using strapping inputs

REFCLK_CONF[2:0] and m REFCLK2_CONF[2:0].

PLL and PLL2 can be used as a recovered clock sources for Synchronous Ethernet. For information

about how to configure PLL and PLL2 clock recovery, see Layer 1 Timing, page 277.

VSC7440 Datasheet(PDF) 319 Page - Microsemi Corporation

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