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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

305

VCore-III System and CPU Interfaces

This section provides information about the functional aspects of blocks and interfaces related to the

VCore-III on-chip microprocessor system and an external CPU system.

The device contains a powerful VCore-III CPU system that is based on an embedded MIPS24KEc-

compatible microprocessor and a high bandwidth Ethernet Frame DMA engine. The VCore-III system

can control the device independently, or it can support an external CPU, relieving the external CPU of the

otherwise time consuming tasks of transferring frames, maintaining the switch core, and handling

networking protocols.

When the VCore-III CPU is enabled, it either automatically boots up from serial Flash or a external CPU

can manually load a code-image to the device and then start the VCore-III CPU.

An external CPU can be connected to the device through the PCIe interface, serial interface (SI),

dedicated MIIM slave interface, or through Versatile Register Access Protocol (VRAP) formatted

Ethernet frames using the NPI Ethernet port. Through these interfaces, the external CPU has access to

the complete set of device registers and can control them without help from the VCore-III CPU if needed.

The following illustration shows the VCore-III block diagram.

Figure 99 •

VCore-III System Block Diagram

Switch Core

Access/Arbiter

Switch Core Register Bus (CSR)

Switch Core

Registers

VCore SBA

Access Block

VCore Shared Bus

Access/Arbiter

VCore Shared Bus (SBA)

GPIO I/O

Controller

MIIM

Masters × 2

Temperature

Sensor

Fan

Controller

SGPIO I/O

Controller

DDR3/3L

Controller

Two-Wire Serial

Interface × 2

UART × 2

Interrupt

Controller

SI Flash Boot

Master(1)

Timers × 3

PCIe Inbound(2)

PCIe

Outbound

VRAP

(Register access

through Ethernet)

Switch Core

Access Block

VCore CPU

MIIM Slave

SI Slave(1)

Frame DMA

(FDMA)

Manual Frame

Inject/Extract

1. When the Vcore-III CPU boots up from the SI Flash, the SI is reserved as boot interface and cannot be used by an external CPU.

2. Inbound PCIe access to BAR0 maps to VCore register space (switch core access block, interrupt controller, timers, two-wire serial

master/slave, UARTs, and manual frame injection/extraction). Inbound PCIe access to BAR2 maps to the DDR3/3L memory space

(DDR controller).

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