VSC7440 datasheet(318/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

301

3.34.2

Link Aggregation

For both ring protection and linear protection, the working/protection entity can be forwarded on a LAG,

providing an additional layer of hardware assisted protection switching.

When a link within the LAG fails, the 16 port masks in ANA_AC:AGGR must be updated to avoid

forwarding on the failed link.

To avoid consuming multiple entries in VCAP ES0 for services being forwarded on a LAG,

REW:COMMON:PORT_CTRL.ES0_LPORT_NUM must be setup such that a common port number is

used in VCAP ES0 keys, regardless of the actual LAG member chosen.

3.34.3

Port Protection Switching

The device supports several methods through which 1:1 port protection switching can be supported:

•

Link Aggregation Groups. A LAG with two ports can be configured and ANA_AC:AGGR can be set

to only use one of the links in the LAG.

•

Disabling the standby port in ANA_L3:MSTP.

•

Disabling the standby port using ANA_L3:COMMON:PORT_FWD_CTRL and

ANA_L3:COMMON:PORT_LRN_CTRL. This is the recommended approach, because it interferes

minimally with other features of the device.

Regardless of the method, a logical port number must be configured for the involved ports such that MAC

addresses are learned on the logical port number to avoid the need for flushing MAC table entries when

protection switching occurs. The logical port number is configured in

ANA_CL:PORT:PORT_ID_CFG.LPORT_NUM.

REW:COMMON:PORT_CTRL.ES0_LPORT_NUM must be used to avoid consuming multiple VCAP

ES0 entries. For more information, see Link Aggregation, page 301.

3.35

Low Power Mode

For applications that only use 1G port speeds it is possible to change the switch core to a low power

mode where the operating clock frequency is dropped to one third of the normal clock frequency.

Configuration of the switch core clock frequency is done after reset, before enabling switch ports.

3.35.1

One-Time Configurations for Low Power Mode

For applications that only use 1G port speeds, reconfiguration of the switch core clock frequency is done

in several steps listed in the following:

Configure the switch core clock frequency:

HSIO:PLL5G_CFG:PLL5G_CFG0.CORE_CLK_DIV = 25 (write to all PLLs when

applicable),

HSIO::CLK_CFG.SWC_CLK_DIV2 = 1.

Configure the port calendar using the following procedure:

DSM::TAXI_CAL_CFG[0].CAL_PGM_ENA = 1

for (i=0; i<6; i++) {

DSM::TAXI_CAL_CFG[0].CAL_IDX = i

DSM::TAXI_CAL_CFG[0].CAL_PGM_VAL = i

}

DSM::TAXI_CAL_CFG[0].CAL_PGM_ENA = 1

DSM::TAXI_CAL_CFG[1].CAL_PGM_ENA = 1

for (i=0; i<5; i++) {

DSM::TAXI_CAL_CFG[1].CAL_IDX = i

DSM::TAXI_CAL_CFG[1].CAL_PGM_VAL = i

}

DSM::TAXI_CAL_CFG[1].CAL_PGM_ENA = 1

DSM::TAXI_CAL_CFG[2].CAL_PGM_ENA = 1

for (i=0; i<2; i++) {

DSM::TAXI_CAL_CFG[2].CAL_IDX = i

DSM::TAXI_CAL_CFG[2].CAL_PGM_VAL = i

}

VSC7440 Datasheet(PDF) 318 Page - Microsemi Corporation

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