VSC7440 datasheet(334/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

317

starts an SBA read access, when the read access completes, the result is automatically stored in the

VA_DATA register.

The VA_DATA_INCR register behaves similar to VA_DATA, except that after starting an access, the

VA_ADDR register is incremented by four (so that it points to the next word address in the SBA domain).

Reading from the VA_DATA_INCR register returns the value of VA_DATA, writing to VA_DATA_INCR

overwrites the value of VA_DATA.

Note: By using VA_DATA_INCR, sequential word addresses can be accessed without having to manually

increment the VA_ADDR register between each access.

The VA_DATA_INERT register provides direct access to the VA_DATA value without starting access on

the SBA. Reading from the VA_DATA_INERT register returns the value of VA_DATA, writing to

VA_DATA_INERT overwrites the value of VA_DATA.

The VCore-III shared bus is capable of returning error-indication when illegal register regions are

accessed. If a VA access results in an error-indication from the SBA, the VA_CTRL.VA_ERR field is set,

and the VA_DATA is set to 0x88888888.

Note: Note SBA error indications only occur when non-existing memory regions or illegal registers are

accessed. This will not happen during normal operation, so the VA_CTRL.VA_ERR indication is useful

during debugging only.

Example Reading from ICPU_CFG::GPR[1] through the VA registers. The GPR register is the second

(and discard the read value). Wait until VA_CTRL.VA_BUSY is cleared, then VA_DATA contains the

value of the ICPU_CFG::GPR[1] register. Using VA_DATA_INERT (instead of VA_DATA) to read the data

is appropriate, because this does not start a new SBA access.

4.5.4.1

Optimized Reading

VCore-III shared bus access is typically much faster than the CPU interface, which is used to access the

VA registers. The VA_DATA register (VA_DATA_INCR and VA_DATA_INERT) return 0x88888888 while

VA_CTRL.VA_BUSY is set. This means that it is possible to skip checking for busy between read access

to SBA. For example, after initiating a read access from SBA, software can proceed directly to reading

from VA_DATA, VA_DATA_INCR, or VA_DATA_INERT

•

If the second read is different from 0x88888888, then the second read returned valid read data (the

SBA access was done before the second read was performed).

•

If the second read is equal to 0x88888888, then the VA logic may have been busy during the read

and additional actions are required: First read the VA_CTRL.VA_BUSY field until the field is cleared

(VA logic is not busy). Then read VA_DATA_INERT. If VA_DATA_INERT returns 0x88888888, then

read-data is actually 0x88888888, continue to the next read. Otherwise, repeat the last read from

VA_DATA, VA_DATA_INCR, or VA_DATA_INERT and then continue to the next read from there.

Optimized reading can be used for single read and sequential read access. For sequential reads, the

VA_ADDR is only incremented on successful (non-busy) reads.

4.5.5

Mailbox and Semaphores

This section provides information about the semaphores and mailbox features for CPU to CPU

communication. The following table lists the registers associated with mailbox and semaphores.

Table 235 •

Mailbox and Semaphore Registers

Description

DEVCPU_ORG::MAILBOX_SET

Atomic set of bits in the mailbox register.

DEVCPU_ORG::MAILBOX_CLR

Atomic clear of bits in the mailbox register.

DEVCPU_ORG::MAILBOX

Current mailbox state.

DEVCPU_ORG::SEMA_CFG

Configuration of semaphore interrupts.

DEVCPU_ORG::SEMA0

Taking of semaphore 0.

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