VSC7440 datasheet(339/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

322

After the root complex has configured the PCIe endpoint’s MSI Capability Register Set and the external

CPU has configured how interrupts from the VCore-III interrupt controller are propagated to PCIe,

interrupts must then be enabled by setting PCIE_INTR_COMMON_CFG.PCIE_INTR_ENA.

4.6.5

Outbound Access

After the PCIe endpoint is initialized, outbound read/write access to PCIe memory space is initiated by

reading or writing the SBA’s PCIe DMA region.

The following table lists the device registers associated with PCIe outbound access.

The PCIe DMA region is 1 gigabyte. Access in this region is mapped to any 1 gigabyte region in 32-bit or

64-bit PCIe memory space by using address translation. Two address translation regions are supported.

The recommended approach is to configure the first region for SBA outbound access and the second

region for FDMA outbound access.

Address translation works by taking bits [29:0] from the SBA/FDMA address, adding a configurable

offset, and then using the resulting address to access into PCIe memory space. Offsets are configurable

in steps of 64 kilobytes in the ATU_TGT_ADDR_HIGH and ATU_TGT_ADDR_LOW registers.

The software on the VCore-III CPU (or other SBA masters) can dynamically reconfigure the window as

needed; however, the FDMA does not have that ability, so it must be disabled while updating the 1

gigabyte window that is set up for it.

Note: Although the SBA and FDMA both access the PCIe DMA region by addresses 0xC0000000 though

0xFFFFFFFF, the PCIe address translation unit can differentiate between these accesses and apply the

appropriate translation.

4.6.5.1

Outbound SBA Translation Region Configuration

Configure PCIESLV_SBA.SBA_OFFSET = 0 and select address translation region 0 by writing

ATU_REGION.ATU_IDX = 0. Set PCIE::ATU_BASE_ADDR_LOW.ATU_BASE_ADDR_LOW = 0x0000

and PCIE::ATU_LIMIT_ADDR.ATU_LIMIT_ADDR = 0x3FFF.

The following table lists the appropriate PCIe headers that must be configured before using the SBA’s

PCIe DMA region. Remaining header fields are automatically handled.

Table 239 •

Outbound Access Registers

Description

ICPU_CFG::PCIESLV_SBA

Configures SBA outbound requests.

ICPU_CFG::PCIESLV_FDMA

Configures FDMA outbound requests.

PCIE::ATU_REGION

Select active region for the ATU_* registers.

PCIE::ATU_CFG1

Configures TLP fields.

PCIE::ATU_CFG2

Enable address translation.

PCIE::ATU_TGT_ADDR_LOW

Configures outbound PCIe address.

PCIE::ATU_TGT_ADDR_HIGH

Configures outbound PCIe address.

Table 240 •

PCIe Access Header Fields

Header Field

Attributes

ATU_CFG1.ATU_ATTR

Poisoned Data

PCIESLV_SBA.SBA_EP

TLP Digest Field Present

ATU_CFG1.ATU_TD

Traffic Class

ATU_CFG1.ATU_TC

Type

ATU_CFG1.ATU_TYPE

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