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VSC7440 Datasheet(PDF) 405 Page - Microsemi Corporation

Part # VSC7440
Description  L2/L3 Enterprise Gigabit Ethernet Switch with 10 Gbps Links
PDF  444 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC7440 Datasheet(HTML) 405 Page - Microsemi Corporation

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Electrical Specifications
VMDS-10492 VSC7440 Datasheet Revision 4.2
388
The 10 Gbps receiver operating in 10GBASE-KR mode complies with IEEE 802.3 clause 72.7.
6.2.6
Reset Timing
The nRESET signal waveform and the required measurement points for the timing specification are
shown in the following illustration.
Figure 135 •
nRESET Signal Timing Specifications
The signal applied to the nRESET input must comply with the specifications listed in the following table at
the reset pin of the device.
Duty cycle distortion (part of
DJ)
DCD
0.035
UIP-P
Total jitter
TJ
0.281
UIP-P
1.
This value is met when the device’s maximum junction temperature is below 110 °C.
2.
IEEE 802.3 section 72.7 states 0.15 UIP-P maximum random jitter.
Table 306 •
10GBASE-KR Receiver
Parameter
Symbol
Minimum
Maximum
Unit
Condition
Data rate
10.3125 – 100 ppm
10.3125 + 100 ppm
Gbps
Differential input
return loss
RLISDD11
–9
dB
50 MHz to 2.5 GHz
Differential input
return loss
RLISDD11
–9 + 12 x log
(ƒ/2.5 GHz)
dB
2.5 MHz to 7.5 GHz
Table 307 •
nRESET Timing Specifications
Parameter
Symbol
Minimum
Maximum
Unit
nRESET assertion time after power supplies and clock
stabilizes
tW
2ms
Recovery time from reset inactive to device fully active
tREC
10
ms
nRESET pulse width
tW(RL)
100
ns
Hold time for GPIO-mapped strapping pins relative to
nRESET
tHCFG
50
ns
Table 305 •
10GBASE-KR Transmitter (continued)
Parameter
Symbol
Minimum
Maximum
Unit
Condition
VDDx
nRESET
tW
VDDxmin
tW(RL)
tREC
tREC
REFCLK
tHCFG
Strapping
tHCFG



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