VSC7440 datasheet(409/444 Pages) MICROSEMI

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Electrical Specifications

VMDS-10492 VSC7440 Datasheet Revision 4.2

392

All SI signals comply with the specifications shown in the following table. The SI input timing

requirements are requested at the pins of the device.

Figure 140 •

SI_DO Disable Test Circuit

6.2.11

DDR SDRAM Interface

This section provides the AC characteristics for the DDR3 and DDR3L SDRAM interface.

The following illustration shows the DDR3/DDR3L SDRAM input timing diagram.

Figure 141 •

DDR SDRAM Input Timing Diagram

Table 311 •

SI Timing Specifications for Slave Mode

Parameter

Symbol Minimum

Maximum

Unit

Condition

Clock frequency

MHz

Clock cycle time

Clock time high

tW(CH)

Clock time low

tW(CL)

SI_DI setup time to clock

tSU(DI)

4ns

SI_DI hold time from clock

tH(DI)

4ns

Enable active before first clock

tLEAD

Enable inactive after clock (input cycle)1

tLAG1 is defined only for write operations to the device, not for read operations.

tLAG1

Enable inactive after clock (output cycle) tLAG2

See note2

The last rising edge on the clock is necessary for the external master to read in the data. The lag time depends on the necessary

hold time on the external master data input.

Enable inactive width

tW(EH)

SI_DO valid after clock

tV(C)

CL =30 pF.

SI_DO hold time from clock

tH(DO)

0ns

CL =0 pF.

SI_DO disable time3

Pin begins to float when a 300 mV change from the loaded VOH or VOL level occurs.

tDIS1

See Figure 139, page 391.

SI_DO disable time3

tDIS2

See Figure 139, page 391.

5 pF

3.3 V

From Output Under Test

500

tCLK

t90

DDR_UDQSn/DDR_LDQSn

DDR_UDQS/DDR_LDQS

DDR_DQ[15:0]

tDH

tDS

tDH

tDS

t90

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