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VSC7440 Datasheet(PDF) 412 Page - Microsemi Corporation

Part # VSC7440
Description  L2/L3 Enterprise Gigabit Ethernet Switch with 10 Gbps Links
PDF  444 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC7440 Datasheet(HTML) 412 Page - Microsemi Corporation

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Electrical Specifications
VMDS-10492 VSC7440 Datasheet Revision 4.2
395
Figure 144 •
JTAG Interface Timing Diagram
All JTAG signals comply with the specifications in the following table. The JTAG receive signal
requirements are requested at the pin of the device.
The JTAG_nTRST signal is asynchronous to the clock and does not have a setup or hold time
requirement.
The following illustration shows the test circuit for the TDO disable time.
Figure 145 •
Test Circuit for TDO Disable Time
Table 314 •
JTAG Interface AC Specifications
Parameter
Symbol
Minimum
Maximum
Unit
Condition
JTAG_TCK frequency
ƒ
10
MHz
JTAG_TCK cycle time
tC
100
ns
JTAG_TCK high time
tW(CH)
40
ns
JTAG_TCK low time
tW(CL)
40
ns
Setup time to JTAG_TCK rising
tSU
10
ns
Hold time from JTAG_TCK rising
tH
10
ns
TDO valid after JTAG_TCK falling
tV(C)
28
ns
CL =10pF
TDO hold time from JTAG_TCK falling
tH(TDO)
0ns
CL =0pF
JTAG_TDO disable time1
1.
The pin begins to float when a 300 mV change from the actual VOH/VOL level occurs.
tDIS
30
ns
See Figure 145,
page 395.
JTAG_nTRST time low
tW(TL)
30
ns
JTAG_TCK
JTAG_TDI
JTAG__TMS
JTAG_TDO
JTAG_nTRST
tC
tW(TL)
tW(CH)
tW(CL)
tH(TDO)
tH
tDIS
See definition
tSU
tV(C)
5 pF
From Output
Under Test
3.3 V
500
Ω
500
Ω



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