VSC7440 datasheet(410/444 Pages) MICROSEMI

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Electrical Specifications

VMDS-10492 VSC7440 Datasheet Revision 4.2

393

The following table lists the AC specifications for the DDR3 and DDR3L SDRAM input signals.

The following illustration shows the timing diagram for the DDR3 and DDR3L SDRAM outputs.

Figure 142 •

DDR SDRAM Output Timing Diagram

Table 312 •

DDR3/DDR3L SDRAM Input Signal AC Characteristics

Parameter

Symbol Minimum

Typical

Maximum

Unit Condition

DDR3 input voltage high

VIH(AC)

DDR_VREF +0.175

VDD_IODDR +0.3

DDR3 input voltage low

VIL(AC)

–0.3

DDR_VREF –0.175 V

DDR3 differential input

voltage

VID(AC)

0.4

VDD_IODDR

DDR3 differential

crosspoint voltage

VIX(AC)

0.5 × VDD_IODDR –

0.175

0.5 × VDD_IODDR +

0.175

DDR3L input voltage high

VIH(AC)

DDR_VREF +0.160

VDD_IODDR +0.3

DDR3L input voltage low

VIL(AC)

–0.3

DDR_VREF –0.160 V

DDR3L differential input

voltage

VID(AC)

0.4

VDD_IODDR

DDR3L differential

crosspoint voltage

VIX(AC)

0.5 × VDD_IODDR –

0.160

0.5 × VDD_IODDR +

0.160

DDR_DQ[7:0] input setup

time relative to

DDR_LDQS1

These requirements are dependent on the operation frequency of the DDR SDRAM interface. Stated limits are for DDR3-800.

tDS

350

DDR_DQ[15:8] input setup

time relative to

DDR_UDQS1

tDS

350

DDR_DQ[7:0] input hold

time relative to

DDR_LDQS1

tDH

250

DDR_DQ[15:8] input hold

time relative to

DDR_UDQS1

tDH

250

Quarter period offset from

clock edge

t90

0.25 × tCLK

tCLK =3.2 ns

tCLK

DDR_CKn

DDR_CK

DDR_DQ[15:0]

DDR_LDM/UDM

DDR_LDQS

DDR_UDQS

R_Addr, DDR_BA/DDR_CKE,

DDR_nRAS, DDR_nCAS,

DR_nWE, DDR_nCS

tDQSPRE

tDQSPST

tCLKDQS

tAH/CH

tAS/CS

tDS tDH

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