VSC7440 datasheet(411/444 Pages) MICROSEMI

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Electrical Specifications

VMDS-10492 VSC7440 Datasheet Revision 4.2

394

The following table lists the AC characteristics for the DDR3 and DDR3L SDRAM output signals.

The following illustration shows the test load circuit for the DDR3 outputs.

Figure 143 •

Test Load Circuit for DDR3 Outputs

6.2.12

JTAG Interface

All AC specifications for the JTAG interface meet or exceed the requirements of IEEE 1149.1-2001.

The following illustration shows the JTAG transmit and receive waveforms and required measurement

points for the different signals.

Table 313 •

DDR3/DDR3L SDRAM Output Signal AC Characteristics

Parameter

Symbol

Minimum

Typical

Maximum

Unit

DDR_CK cycle time 312.5 MHz

(DDR800)1

Timing reference is DDR_CK/DDR_CKn crossing ±0.1 V.

tCLK

3.20

DDR_CK/CKn duty cycle

DDR_A, DDR_BA, DDR_CKE,

DDR_nRAS, DDR_nCAS, and DDR_nWE

output setup time relative to DDR_CK/CKn

tAS

700

DDR_A, DDR_BA, DDR_CKE,

DDR_nRAS, DDR_nCAS, and DDR_nWE

output hold time relative to DDR_CK/CKn

tAH

800

DDR_CK/CKn to DDR_DQS skew

tCLKDQS

–400

400

DDR_DQ[7:0]/DDR_LDM output setup

time relative to DDR_LDQS

tDS

400

DDR_DQ[15:8]/DDR_UDM output setup

time relative to DDR_UDQS

tDS

400

DDR_DQ[7:0]/DDR_LDM output hold time

relative to DDR_LDQS

tDH

500

DDR_DQ[15:8]/DDR_UDM output hold

time relative to DDR_UDQS

tDH

500

DDR_DQS preamble start

tDQSPRE

0.4 × tCLK

0.6 × tCLK

DDR_DQS postamble end

tDQSPST

0.4 × tCLK

0.6 × tCLK

Outputs

0.5 × VDD_IODDR

150

ZO = 60 Ω

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