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VCore-Ie System and CPU Interfaces

VMDS-10488 VSC7511 Datasheet Revision 4.2

166

The following table lists the registers associated with starting up the VCore-Ie CPU.

The VCORE_CFG strapping pins determine if the VCore-Ie CPU boots up automatically or if it is kept in

reset after startup. For more information, see VCore-Ie Configurations, page 159.

4.3.5.1

Loading On-Chip Memory

The basic principle of loading the on-chip memory is the same whether the VCore-Ie CPU is copying

from Flash during automatic booting or if an external CPU is manually loading a code-image.

The initial step of loading on-chip memory is to set up a source address in the shared bus domain by

writing to MEMACC_SBA.MEMACC_SBA_START. For automatic booting, this is typically address

0x00000000 (the first address in the Flash). When manually loading on-chip memory from an external

CPU, a good choice for transferring data is the eight 32-bit general-purpose registers (GPR), starting at

address 0x70000000.

The second step is to configure destination-range in the on-chip memory by using

MEMACC.MEMACC_START and MEMACC.MEMACC_STOP.

A transfer is started by writing to MEMACC_CTRL.MEMACC_DO. This field is cleared when all (32-bit)

words in the range MEMACC_START through MEMACC_STOP are copied. When MEMACC_START is

equal to MEMACC_STOP, only one word is copied. Word addresses are incremented for each word that

is copied (the registers are not physically changed). This means that the n’th word in a given transfer is

copied between addresses MEMACC_AHB_START.MEM_ACC_START+n and

MEMACC.MEMACC_START+n.

When loading from Flash, the entire on-chip memory can be filled using one long transfer. When loading

from an external CPU using the GPR registers, the external CPU repeat transferring blocks of code until

the entire code-image is copied to on-chip memory.

The clock of the VCore-Ie CPU is gated during loading of the on-chip memory, which means that loading

of the on-chip memory is instantaneous (from the point of view of the software running on the VCore-Ie

CPU).

By setting MEMACC_CTRL.MEMACC_EXAMINE, the direction of the transfer can be changed, which

allows an external CPU to examine the contents of the on-chip memory instead of loading it.

Loading of the on-chip memory is not limited to copying code during booting. Whenever code or data

must be copied from Flash to on-chip memory, the hardware for loading the on-chip memory can be

used. The on-chip memory area can be loaded while the VCore-Ie CPU is operating.

Example: Manually Loading 58 Bytes of Code to On-Chip Memory. This example uses all eight GPR

registers for transferring data to on-chip memory. Configure the MEMACC_AHB register to 0x70000000

(the address of the first GPR register). Write the first 32 bytes of code to GRP[0] though GPR[7]. Set the

destination range to the first 8 words of on-chip memory by writing 0x001C0000 to the MEMACC register.

Write to MEMACC_CTRL.MEMACC_DO to start the access, make sure that

MEMACC_CTRL.MEMACC_EXAMINE is cleared. The MEMACC_DO field is automatically cleared

when the transfer is done, when this happens the next 26 bytes can be written to GRP[0] though GPR[6]

(only byte addresses 0 and 1 of GPR[6] is used). Update the destination range in on-chip memory by

writing 0x00380020 to the MEMACC register. Start the second transfer by writing to

Table 132 •

VCore-Ie CPU Startup Registers

Description

RESET

Manual release of VCore-Ie CPU reset

MPU8051_MMAP

Mapping of on-chip memory

MEMACC_CTRL

Starting copy of memory regions

MEMACC

Configuration of on-chip memory address range

MEMACC_SBA

Configuration of SBA start address

GPR

Set of eight general-purpose 32-bit registers

VSC7511 Datasheet(PDF) 181 Page - Microsemi Corporation

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