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VCore-Ie System and CPU Interfaces

VMDS-10488 VSC7511 Datasheet Revision 4.2

167

MEMACC_CTRL.MEMACC_DO. After this field is cleared, the code is copied. The on-chip memory can

then be mapped, and the VCore-Ie CPU can be released from reset.

4.3.5.2

Mapping On-Chip Memory

By default, the on-chip memory is transparent to the VCore-Ie CPU. Using the MPU8051_MMAP or the

SFR::MMAP registers, the on-chip memory can be mapped into code and data space of the VCore-Ie

CPU.

There are two MMAP registers: one that is part of the VCore-Ie registers (MPU8051_MMAP) and one

that is a part of the 8051’s SFR registers (SFR::MMAP). The mapping of on-chip memory is the result of

a bit-wise OR between these two registers. Only one of these registers must be used.

When manually loading a code-image from an external CPU, the MPU8051_MMAP register must be

used. When automatically booting up from Flash, use the SFR::MMAP register. The encoding of these

two registers are the same, and both registers are commonly referred to as MMAP.

The MPU8051_MMAP register in the VCore-Ie registers can be protected from VCore-Ie soft-reset.

When the MPU8051_MMAP register is used, and the VCore-Ie system is protected from reset, the

mapping remains active after soft-reset of the VCore-Ie CPU.

The code interface of the 8051 maps to the shared bus by default. Setting MMAP.MAP_CODE_LOW

maps access in the low 32 kilobyte region of the code interface to the on-chip memory. Setting

MMAP.MAP_CODE_HIGH maps access in the high 32 kilobyte region of the code interface to the on-

chip memory.

MMAP.MSADDR_CODE_LOW controls if either the lower or higher half of the on-chip memory is

accessed when the low 32 kilobyte region of the code interface maps an access to on-chip memory.

MMAP.MSADDR_CODE_HIGH controls if either lower or higher half of the on-chip memory is accessed

when the high 32 kilobyte region of the code interface maps an access to the on-chip memory.

The data interface of the 8051 maps to the shared bus by default. Setting MMAP.MAP_DATA_LOW

maps access in the low 32 kilobyte region of the data interface to the on-chip memory. Setting

MMAP.MAP_DATA_HIGH maps access in the high 32 kilobyte region of the data interface to the on-chip

memory.

MMAP.MSADDR_DATA_LOW controls if either the lower or higher half of the on-chip memory is

accessed when the low 32 kilobyte region of the data interface maps an access to the on-chip memory.

MMAP.MSADDR_DATA_HIGH controls if either the lower or higher half of the on-chip memory is

accessed when the high 32 kilobyte region of the data interface maps an access to the on-chip memory.

Example: Map the Complete On-Chip Memory to Both Code and Data. Some 8051 compilers support

using the same physical memory for both code and data. To map the complete 64 kilobyte on-chip

memory to both code and data interfaces, set MMAP to 0xAF. Then a code access on address n and a

data access on address n both maps to an access on address n inside the on-chip memory.

Example: Split On-Chip Memory between Code and Data. In some cases, it may be desirable to use non-

overlapping memory for code and data. Setting MMAP to 0x15 maps the lower half of the on-chip

memory to the code interface and the higher half to the data interface. Code address n then maps to

address n inside the on-chip memory, and data address n maps to address n+0x8000 inside the on-chip

memory.

4.3.6

Accessing the VCore-Ie Shared Bus

Access to the VCore-Ie shared bus is done through registers in the Special Function Registers (SFR)

domain of the VCore-Ie CPU.

The following table lists the registers associated with the VCore-Ie shared bus.

Table 133 •

Shared Bus Access (SBA) Registers

Description

SFR::RA_AD0_RD

SBA address[7:0], and read access initiation

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