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VCore-Ie System and CPU Interfaces

VMDS-10488 VSC7511 Datasheet Revision 4.2

168

During access to the VCore-Ie shared bus, the clock of the VCore-Ie CPU is gated. This means that from

the point of view of the software, access to the shared bus is instantaneous.

Although the shared bus is byte-addressable, the VCore-Ie always does word access (reading or writing

32 bits of data). As a result, the shared bus address must be a word-aligned address, meaning that the

two least significant bits of the address must always be 0.

Reading from the VCore-Ie shared bus requires configuration of read-address by writing to RA_AD3,

RA_AD2, RA_AD1, followed by write to RA_AD0_RD. The last write initiates the read access. The

registers RA_DA3, RA_DA2, RA_DA1, and RA_DA0 are overwritten with the result of the read access.

Note Because shared bus accesses are instantaneous, from software perspective, the data is available

to the instruction immediately following the write to RA_AD0_RD.

Writing to the VCore-Ie shared bus requires setting up write-data in RA_DA3, RA_DA2, RA_DA1, and

RA_DA0, configuration of write-address by writing to RA_AD3, RA_AD2, RA_AD1, followed by write to

RA_AD0_WR. The last write initiates the write access.

The only registers that can be modified by hardware are the RA_DA* registers and these are only

changed during read operations.

Example: Copy ICPU_CFG::GPR[1] to ICPU_CFG::GPR[2] with change to 4'th byte. Perform read by

setting RA_AD3=0x70, RA_AD2=0x00, RA_AD1=0x00, and RA_AD0_RD=0x04. The RA_DA3,

RA_DA2, RA_DA1, and RA_DA0 registers have now been updated with the value of

ICPU_CFG::GPR[1]. Modify RA_DA3 (the 4'th byte), and set RA_AD0_WR=0x08 to save to

ICPU_CFG::GPR[2].

4.3.7

Paged Access to VCore-Ie Shared Bus

The VCore-Ie CPU supports paged access to the shared bus. Paging extends the address space of the

VCore-Ie CPU by 8 bits, thereby increasing the addressable region from 64 kilobytes to 16 megabytes.

The following table lists the registers associated with paged access to the VCore-Ie shared bus.

The paging mechanism of the VCore-Ie CPU only applies to access to the shared bus; the paging

registers (PG and EPG) does not affect code or data access that are mapped to on-chip memory.

The PG register contains two groups: IFP[3:0] and OP[3:0]. The IFP group holds four page bits used for

instruction fetches and program memory reads (MOVC instructions). The OP group holds four page bits

used for all other types of external memory accesses. The layout of the EPG and EEPG registers are

SFR::RA_AD0_WR

SBA address[7:0], and write access initiation

SFR::RA_AD1

SBA address[15:8]

SFR::RA_AD2

SBA address[23:16]

SFR::RA_AD3

SBA address[31:24]

SFR::RA_DA0

SBA data[7:0]

SFR::RA_DA1

SBA data[15:8]

SFR::RA_DA2

SBA data[23:16]

SFR::RA_DA3

SBA data[31:24]

Table 134 •

Paged Access to VCore-Ie Shared Bus

Description

SFR::PG

Paging Control

SFR::EPG

Extended Paging Control

Table 133 •

Shared Bus Access (SBA) Registers (continued)

Description

VSC7511 Datasheet(PDF) 183 Page - Microsemi Corporation

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