M62023P datasheet(4/4 Pages) MITSUBISHI

4 / 4 page

MITSUBISHI <Dig./Ana.INTERFACE>

SYSTEM RESET IC WITH SWITCH FOR MEMORY BACK-UP

M62023L,P,FP

1997.5.30- rev

(

)

PRELIMINARY

Notice:This

is not

a final

specification.

Some

parametric

limits

are

subject

to change.

TIMING CHART

V1=VIN-VDROP

V2=VIN-VEB(SW Tr.)

V3=VBAT-VF

VSH

VSL

∆VS

tpd

VIN

VOUT

VIN(VSL)

VOL(CS)

VOL(RES)

VIN(VSL)

VOH(RES)

RES

As the state shifts from a logic

high to logic low, the output

level becomes VOL(RES)

The output level is VOL(CS)

with a logic low

The output level is VOH(RES)

with a logic high

In normal operation

Input voltage : 3V

Input

voltage

VOUT

RES

Output

With SW Tr. set to ON, a

voltage (VIN-VDROP) is output

The output level is VOL(RES)

with a logic low

In failure

(instantaneous drop)

Input voltage : 3V

Each output varies if the input

voltage drops to VSL or under

SW Tr. is turned OFF. A

voltage (VIN-VEB) is output by

the diode between E and B of

SW Tr.

As the state shifts from a logic

low to logic high, the output

level becomes approximately

equal to the input voltage

Restoration from failure

(instantaneous drop)

Input voltage : 2V

If the input voltage goes higher

than VSL by 100mV, each

output varies after delay

produced by the delay circuit

SW Tr. is turned ON after delay

and a voltage (VIN-VDROP) is

output

A logic high is maintained, and

then shifts to a logic low

In backup state

Input voltage : 0V

Backup voltage : 3V

VBAT-VF

The output is a logic high and

the output level is VBAT-VF

As the state shifts from a logic

low to logic high, the output

level becomes the voltage

VIN-VEB

A logic low is maintained, and

then shifts to a logic high

A logic high is maintained, and

then shifts to a logic low

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