PMC232 datasheet(39/94 Pages) PADAUK

39 / 94 page

PMC232/PMS232 Series

12-bit ADC Enhanced FPPA

8-bit OTP Controller

Page 39 of 94

PDK-DS-PMx232_V104– Dec. 18, 2018

void FPPA0 (void)

{

. ADJUST_IC

SYSCLK=IHRC/16, IHRC=16MHz, VDD=5V, Band-gap=On

// If Band-gap is not calibrated, it can use “. ADJUST_IC

DISABLE” ...

EOSCR

Enable, 4MHz;

// EOSCR = 0b110_00000;

T16M

EOSC, /1, BIT13;

// T16 receive 2^14=16384 clocks of crystal EOSC,

// Intrq.T16 =>1, crystal EOSC Is stable

WORD

count

stt16count;

Intrq.T16 =

wait1

Intrq.T16;

// count from 0x0000 to 0x2000, then set INTRQ.T16

clkmd

0xB4;

// switch system clock to EOSC;

Clkmd.4 = 0;

// disable IHRC

...

Please notice that the crystal oscillator should be fully turned off before entering the power-down mode, in

order to avoid unexpected wakeup event. If the 32 KHz crystal oscillator is used and extremely low operating

current is required, misc.6 can be set to reduce current after crystal oscillator is running normally.

5-7-5. System Clock and LVR level

The clock source of system clock comes from EOSC, IHRC and ILRC, the hardware diagram of system clock

in the PMC232/PMS232 is shown as Fig. 9.

Fig.9: Options of System Clock

User can choose different operating system clock depends on its requirement; the selected operating system

clock should be combined with supply voltage and LVR level to make system stable. The LVR level will be

selected during compilation, and the lowest LVR levels can be chosen for different operating frequencies.

Please refer to Section 4.1.

clkmd[7:5]

System

clock

CLK

÷2, ÷4, ÷6,

÷8, ÷16, ÷32, ÷64

÷1, ÷2, ÷4, ÷8

÷1 (default), ÷4

IHRC

clock

ILRC

clock

EOSC

clock

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