PMC232 datasheet(68/94 Pages) PADAUK

68 / 94 page

PMC232/PMS232 Series

12-bit ADC Enhanced FPPA

8-bit OTP Controller

Page 68 of 94

PDK-DS-PMx232_V104– Dec. 18, 2018

6-28. Timer2 Control Register (tm2c), IO address = 0x3c

Bit

Reset

R/W

Description

7 - 4

0000

R/W

Timer2 clock selection.

0000 : disable

0001 : system clock

0010 : internal high RC oscillator (IHRC)

0011 : reserved

0100 : ILRC

0101 : reserved

011x : reserved

1000 : PA0 (rising edge)

1001 : ~PA0 (falling edge)

1010 : PA3 (rising edge)

1011 : ~PA3 (falling edge)

1100 : PA4 (rising edge)

1101 : ~PA4 (falling edge)

Notice: In ICE mode and IHRC is selected for Timer2 clock, the clock sent to Timer2

does NOT be stopped, Timer2 will keep counting when ICE is in halt state.

3–2

R/W

Timer2 output selection.

00 : disable

01 : PA2

10 : PA3

11 : reserved

R/W

Timer2 mode selection.

0 / 1 : period mode / PWM mode

R/W

Enable to inverse the polarity of Timer2 output.

0 / 1: disable / enable.

6-29. Timer2 Counter Register (tm2ct), IO address = 0x3d

Bit

Reset

R/W

Description

7 - 0

0x00

R/W

Bit [7:0] of Timer2 counter register.

6-30. Timer2 Scalar Register (tm2s), IO address = 0x37

Bit

Reset

R/W

Description

PWM resolution selection.

0 : 8-bit

1 : 6-bit

6 - 5

Timer2 clock pre-scalar.

00 : ÷ 1

01 : ÷ 4

10 : ÷ 16

11 : ÷ 64

4 - 0

00000

Timer2 clock scalar.

6-31. Timer2 Bound Register (tm2b), IO address = 0x09

Bit

Reset

R/W

Description

7 - 0

0x00

Timer2 bound register.

PMC232 Datasheet(PDF) 68 Page - PADAUK Technology.

PMC232 Datasheet(HTML) 68 Page - PADAUK Technology.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

Datasheet Download

Link URL