PMS15B datasheet(37/68 Pages) PADAUK

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PMS15B/PMS150G Family

8 bit OTP Type IO Controller

Page 37 of 68

PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020

5.8. Watchdog Timer

The watchdog timer (WDT) is a counter with clock coming from ILRC and its frequency is about 62KHz@5V.

There are 4 different timeout periods of watchdog timer can be chosen by setting the misc register, it is:

 256k ILRC clock period when misc[1:0]=11

 64k ILRC clock period when misc[1:0]=10

 16k ILRC clock period when misc[1:0]=01

 8k ILRC clock period when misc[1:0]=00 (default)

The frequency of ILRC may drift a lot due to the variation of manufacture, supply voltage and temperature; user

should reserve guard band for safe operation. WDT can be cleared by power-on-reset or by command

wdreset at any time. When WDT is timeout, PMS15B/PMS150G will be reset to restart the program execution.

The relative timing diagram of watchdog timer is shown as Fig. 11.

VDD

Time Out

Program

Execution

tSBP

Watch Dog Time Out Sequence

VDD

Time Out

Program

Execution

tSBP

Watch Dog Time Out Sequence

Fig. 11: Sequence of Watch Dog Time Out

PMS15B Datasheet(PDF) 37 Page - PADAUK Technology.