8 Detailed Description

8.1 Overview

The SN74HCS259 8-bit addressable latches are designed for general-purpose storage applications in digital

systems. Specific uses include working registers, serial-holding registers, and active-high decoders or

demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches

and being a 1-of-8 decoder or demultiplexer with active-high outputs.

Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs:

• Addressable-latch mode: CLR = HIGH; G = LOW

– Data at the data-in terminal is written into the addressed latch

– The addressed latch follows the data input, with all unaddressed latches remaining in their previous states

• Memory mode: CLR = HIGH; G = HIGH

– All latches remain in their previous states and are unaffected by the data or address inputs

– To eliminate the possibility of entering erroneous data in the latches, G should be held high (inactive) while

the address lines are changing

• 1-of-8 decoding or demultiplexing mode: CLR = LOW; G = LOW

– The addressed output follows the level of the D input with all other outputs low

• Clear mode: CLR = LOW; G = HIGH

– All outputs are low and unaffected by the address and data inputs

8.2 Functional Block Diagram

CLR

G

3:8 DECODER

001

010

011

100

101

110

111

D

LE

Q

R

D

LE

Q

R

D

LE

Q

R

D

LE

Q

R

D

LE

Q

R

D

LE

Q

R

D

LE

Q

R

D

LE

Q

R

LATCH

ENABLE

D

OUTPUT STORAGE

000

Figure 8-1. Logic Diagram (Positive Logic) for SN74HCS259

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SN74HCS259

SCLS836 – SEPTEMBER 2020

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