IIS2DLPCTR datasheet(48/69 Pages) STMICROELECTRONICS

48 / 69 page

IIS2DLPC

48/69

DocID031788 Rev 4

8.4

CTRL1 (20h)

Control register 1 (r/w)

Table 28. Control register 1

Table 29. Control register 1 description

ODR[3:0] is used to set the power mode and ODR selection. The following table lists the bit

settings for power-down mode and each available frequency.

Table 30. Data rate configuration

Table 31. Mode selection

Table 32. Low-power mode selection

ODR3

ODR2

ODR1

ODR0

MODE1

MODE0

LP_MODE1 LP_MODE0

ODR[3:0]

Output data rate and mode selection (see Table 30)

MODE[1:0]

Mode selection (see Table 31)

LP_MODE[1:0] Low-power mode selection (see Table 32)

ODR[3:0]

Power mode / data rate configuration

0000

Power-down

0001

High-Performance / Low-Power mode 12.5/1.6 Hz

0010

High-Performance / Low-Power mode 12.5 Hz

0011

High-Performance / Low-Power mode 25 Hz

0100

High-Performance / Low-Power mode 50 Hz

0101

High-Performance / Low-Power mode 100 Hz

0110

High-Performance / Low-Power mode 200 Hz

0111

High-Performance / Low-Power mode 400/200 Hz

1000

High-Performance / Low-Power mode 800/200 Hz

1001

High-Performance / Low-Power mode 1600/200 Hz

MODE[1:0]

Mode and resolution

Low-Power Mode (12/14-bit resolution)

High-Performance Mode (14-bit resolution)

Single data conversion on demand mode (12/14-bit resolution)

LP_MODE[1:0]

Power mode and resolution

Low-Power Mode 1 (12-bit resolution)

Low-Power Mode 2 (14-bit resolution)

Low-Power Mode 3 (14-bit resolution)

Low-Power Mode 4 (14-bit resolution)

IIS2DLPCTR Datasheet(PDF) 48 Page - STMicroelectronics

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