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IIS2DLPCTR Datasheet(PDF) 16 Page - STMicroelectronics |
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IIS2DLPCTR Datasheet(HTML) 16 Page - STMicroelectronics |
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16 / 69 page  Mechanical and electrical specifications IIS2DLPC 16/69 DocID031788 Rev 4 2.4.2 I2C - inter-IC control interface Subject to general operating conditions for Vdd and Top. Figure 4. I2C slave timing diagram Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports. Table 8. I2C slave timing values Symbol Parameter I2C standard mode (1) I2C fast mode (1) Unit Min Max Min Max f(SCL) SCL clock frequency 0 100 0 400 kHz tw(SCLL) SCL clock low time 4.7 1.3 μs tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 ns th(SDA) SDA data hold time 0.01 3.45 0.01 0.9 μs th(ST) START condition hold time 4 0.6 μs tsu(SR) Repeated START condition setup time 4.7 0.6 tsu(SP) STOP condition setup time 4 0.6 tw(SP:SR) Bus free time between STOP and START condition 4.7 1.3 1. Data based on standard I2C protocol requirement, not tested in production |
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