SN74LS194A

http://onsemi.com

3

LOGIC DIAGRAM

GND = PIN 8

= PIN NUMBERS

CP

MR

14

1

2

6

7

3

4

5

9

11

12

10

13

15

CP

R

CLEAR

CP

R

CLEAR

CP

R

CLEAR

CP

R

CLEAR

FUNCTIONAL DESCRIPTION

The Logic Diagram and Truth Table indicate the

functional characteristics of the LS194A 4-Bit Bidirectional

Shift Register. The LS194A is similar in operation to the

ON Semiconductor LS195A Universal Shift Register when

used in serial or parallel data register transfers. Some of the

common features of the two devices are described below:

All data and mode control inputs are edge-triggered,

responding only to the LOW to HIGH transition of the Clock

(CP). The only timing restriction, therefore, is that the mode

control and selected data inputs must be stable one set-up

time prior to the positive transition of the clock pulse.

The register is fully synchronous, with all operations

taking place in less than 15 ns (typical) making the device

especially useful for implementing very high speed CPUs,

or the memory buffer registers.

HIGH transition of the clock.

The asynchronous Master Reset (MR), when LOW,

overrides all other input conditions and forces the Q outputs

LOW.

Special logic features of the LS194A design which

increase the range of application are described below:

synchronous operation of the device. As shown in the Mode

Selection Table, data can be entered and shifted from left to

LOW, the existing data is retained in a “do nothing” mode

without restricting the HIGH to LOW clock transition.

the first and last stages to allow multistage shift right or shift

left data transfers without interfering with parallel load

operation.