74LS194 datasheet(5/8 Pages) ONSEMI

5 / 8 page

SN74LS194A

http://onsemi.com

AC SETUP REQUIREMENTS (TA = 25°C)

Limits

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

Clock or MR Pulse Width

Mode Control Setup Time

Data Setup Time

VCC = 5.0 V

Hold time, Any Input

trec

Recovery Time

DEFINITIONS OF TERMS

SETUP TIME(ts) —is defined as the minimum time

required for the correct logic level to be present at the logic

input prior to the clock transition from LOW to HIGH in

order to be recognized and transferred to the outputs.

HOLD TIME (th) — is defined as the minimum time

following the clock transition from LOW to HIGH that the

logic level must be maintained at the input in order to ensure

continued recognition. A negative HOLD TIME indicates

that the correct logic level may be released prior to the clock

transition from LOW to HIGH and still be recognized.

RECOVERY TIME (trec) — is defined as the minimum time

required between the end of the reset pulse and the clock

transition from LOW to HIGH in order to recognize and

transfer HIGH Data to the Q outputs.

AC WAVEFORMS

The shaded areas indicate when the input is permitted to change for predictable output performance.

Figure 1. Clock to Output Delays Clock Pulse

Width and fmax

Figure 2. Master Reset Pulse Width, Master Reset

to Output Delay and Master Reset to Clock

Recovery Time

1.3 V

OTHER CONDITIONS: S1 = L, MR = H, S0 = H

OTHER CONDITIONS: S0, S1 = H

OTHER CONDITIONS: PO = P1 = P2 = P3 = H

OTHER CONDITIONS: MR = H

OTHER CONDITIONS: *DSR SET-UP TIME AFFECTS Q0 ONLY

OTHER CONDITIONS: DSL SET-UP TIME AFFECTS Q3 ONLY

OTHER CONDITIONS: MR = H

DSR DSL

P0 P1 P2 P3

CLOCK

OUTPUT*

(––– IS SHIFT LEFT)

CLOCK

OUTPUT

S0 S1

ts(H)

th(L) = 0

th(H) = 0

ts(H)

th(L) = 0

ts(L)

th = 0

(STABLE TIME)

tPHL

tPLH

1/fmax

ts(L)

trec

tPHL

1.3 V

Figure 3. Setup (ts) and Hold (th) Time for Serial Data

(DSR, DSL) and Parallel Data (P0, P1, P2, P3)

Figure 4. Setup (ts) and Hold (th) Time for S Input

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