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ST7LITE30 Datasheet(PDF) 63 Page - STMicroelectronics |
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ST7LITE30 Datasheet(HTML) 63 Page - STMicroelectronics |
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63 / 167 page  ST7LITE3 63/167 DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) – At the second input capture on the falling edge of the pulse, we assume that the values in the reg- isters are as follows: LTICR = LT2 ATICRH = ATH2 ATICRL = ATL2 Hence ATICR2 [11:0] = ATH2 & ATL2 Now pulse width P between first capture and sec- ond capture will be: P = decimal (F9 – LT1 + LT2 + 1) * 0.004ms + dec- imal (ATICR2 - ATICR1 – 1) * 1ms Figure 44. Long Range Input Capture Timing Diagram 11.2.4 Low Power Modes F9h 00h LT1 F9h 00h LT2 ATH1 & ATL1 00h 0h LT1 ATH1 LT2 ATH2 fOSC/32 TB Counter1 CNTR1 LTIC LTICR ATICRH 00h ATL1 ATL2 ATICRL ATICR = ATICRH[3:0] & ATICRL[7:0] _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ATH2 & ATL2 _ _ _ Mode Description SLOW The input frequency is divided by 32 WAIT No effect on AT timer ACTIVE- HALT AT timer halted except if CK0=1, CK1=0 and OVFIE=1 HALT AT timer halted. 1 |
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