CS91 Series

8

■ INPUT/OUTPUT PIN CAPACITANCE

(f

Note : Capacitance values according to the package and the location of the pin.

■ DESIGN METHOD

Fujitsu’s Reference Design Flow provides the following functions that shorten the development time of large

scale and high quality LSIs.

• High reliability design estimation in the early stage of physical design realized by physical prototyping.

• Layout synthesis with optimized timing realized by physical synthesis tools.

• High accuracy design environment considering drop in power supply voltage, signal noise, delay penalty, and

crosstalk.

• I/O design environment (power line design, assignment and selection of I/Os, package selection) considering

noise.

■ PACKAGES

A variety of package types

Development of chips with narrow-pitch solder bump technology and high-pin count packages enables users to

respond to the high-pin count, high-speed requirements of the network market. A variety of packages from

existing series are also available for smooth transition from previously developed models.

Contact your FUJITSU representative for availability dates.

FCBGA package : maximum 2116 pins

EBGA package

: maximum 672 pins

FBGA package

: maximum 304 pins

QFP package

: maximum 304 pins

Parameter

Symbol

Value

Unit

Input pin

16 Max

pF

Output pin

16 Max

pF

Input/output pin

16 Max

pF