DM8108
8 port 10/100M Fast Ethernet Switching Controller
Preliminary
19
Version: DM8108-DS-P02
November 25, 1999
MII Management
MII Management Registers Serial Access
The MII specification defines a set of 32 16-
bit status and control registers that are
addressable through the serial data interface
pins MDCLK and MDIO. Please refer to a
PHY device’s spec for the definition
of the registers.
The DM8108 will initialize MII management
registers accessing after RESET. In EDO
memory configuration mode, the DM8108
acts as Serial MII initiator.
In SDRAM
memory configuration, only the DM8108
whose device # equals to 0 is the initiator.
Other devices cascaded will be the listener to
extract the auto-negotiation information from
MID stream.
MDCLK has a maximum clock rate of 2.5MHz.
The MDIO line is bi-directional and may be
shared by up to 32 devices. The protocol and
the access waveform are shown below:
MDCLK
z
z
MDIO
(DM8108)
z
z
MDIO
(PHY)
z
0
1
1
0
0
1
1 0
0
0 0
0
0 0
z 0
0
0
1
1
0
0
0
1
0
0 0
0
0 0
0
0
z
adle
start
op code
PHY address
Register address
TR
Register
Data
Figure
Typical MDIO Read Operation
MDCLK
MDIO
z
(DM8108)
z
0
1
0
1
0
1 1
0
0
0
0 0 0 0
1
0
0
0
0
0
0
z
idle
start
op code
PHY address
Register address
TR
Write Data
Figure
Typical MDIO Write Operation
Protocol
<idle><start><op code><device address><register addr.><Turnaround>< data
><idle>
Read Operation
< z
>< 01
><
10
><
xxxxx
><
xxxxx
><
z0
><xxxxh><idle>
Write Operation
< z
>< 01
><
01
><
xxxxx
><
xxxxx
><
10
><xxxxh><idle>
Table
MII Management Serial Protocol
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