LTC6269 datasheet(15/28 Pages) AD

15 / 28 page

LTC6226/LTC6227

Rev 0

For more information www.analog.com

PIN FUNCTIONS

FB (SOIC-8 Only): Feedback Pin. Internally connected to

OUT.

+IN: Non-Inverting Input of Amplifier. Valid input range is

from V– to V+ – 1.2V

–IN: Inverting Input of Amplifier. Valid input range is from

V– to V+ – 1.2V

OUT: Output of the Amplifier. Swings rail to rail and can

typically source/sink 60mA of current.

Circuit Description

The LTC6226/LTC6227 have an input signal range that

extends from the negative power supply to 1.2V below

the positive power supply. Figure 1 depicts a simplified

schematic of the amplifier. The input stage consists of PNP

transistors Q1 and Q2. Bootstrap transistor Q13 improves

DC accuracy by reducing the offset contribution of the

base currents of Q11 and Q12 since it has twice their col-

lector current thus Q11/Q12 current matching becomes

SHDN: Shutdown Pin (Active Low). Referenced to V+.

When taken 2.75V below V+, the amplifier shuts down

and enters low power mode, with the outputs in a high

impedance state. When left floating, the amplifier is on.

V+: Positive Supply to Amplifier. Valid range is from 2.8V

to 11.75V when V– is 0V.

V–: Negative Supply to Amplifier. Typically 0V. This can

be made a negative voltage as long as 2.8V ≤ (V+ – V–)

≤ 11.75V

independent of transistor β. The bootstrap arrangement

also enhances gain by improving output impedance. A

pair of complementary common emitter stages, Q15 and

Q14, enables the output to swing to either rail. The SHDN

Interface block translates the SHDN signal into pwr_dn

for powering down the device (by deactivating current

sources I1 - I4) and putting the output in a high impedance

state (by shorting the bases of Q15/Q14 to the supplies

via M2 and M1).

APPLICATIONS INFORMATION

Figure 1. LTC6226/LTC6227 Simplified Schematic Diagram

SHDN

62267 F01

V+

V–

V+

V–

Q15

Q11

+IN

ESDD1

SHDN

INTERFACE

BLOCK

pwr_dn

+IN

ESDD4

ESDD6

ESDD5

OUT

V+

V–

ESDD3

ESDD2

Q10

Q14

Q13

Q12

BUFFER

AND

OUTPUT BIAS

pwr_dn

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