LTC6269 datasheet(17/28 Pages) AD

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LTC6226/LTC6227

Rev 0

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APPLICATIONS INFORMATION

Figure 2. 7pF Feedback Cancels Parasitic Pole

Feedback Components

When feedback resistors are used to set up gain, care

must be taken to ensure that the pole formed by the feed-

back resistors and the parasitic capacitance at the invert-

ing input does not degrade stability. For example if the

amplifier is set up in a gain of +2 configuration with gain

and feedback resistors of 1k, a parasitic capacitance of

7pF (device + PC board) at the amplifier’s inverting input

will cause the part to oscillate, due to a pole formed at

45MHz. An additional capacitor of 7pF across the feedback

resistor as shown in Figure 2 will eliminate any ringing or

oscillation. In general, if the resistive feedback network

results in a pole whose frequency lies within the closed

loop bandwidth of the amplifier, a capacitor can be added

in parallel with the feedback resistor to introduce a zero

whose frequency is close to the frequency of the pole,

improving stability. For high speed designs, minimizing

parasitic inductance is important. The use of capacitors

where the electrodes are terminated on the long side

instead of the short side (for example the use of 0306

instead of 0603 components) can help in this regard.

Power Dissipation

Care must be taken to ensure that the junction tempera-

ture of the die does not exceed 150°C.

The junction temperature, TJ, is calculated from the ambi-

ent temperature, TA, power dissipation, PD, and thermal

resistance, θJA:

TJ = TA + (PD • θJA).

The power dissipation in the IC is a function of the supply

voltage, output voltage and load resistance. For symmet-

ric supply voltages with output load connected to ground,

the worst-case power dissipation PD(MAX) occurs when

the supply current is maximum and the output voltage at

half of either supply voltage for a given load resistance.

PD(MAX) is approximately (since IS actually changes with

output load current) given by:

PD(MAX) = (2 • VS • IS(MAX)) + (VS/2)2/RL

Example: For an LTC6227 in a 8-lead MS package operat-

ing on ±5V supplies and driving a 250Ω load to ground,

the worst-case power dissipation is approximately given

by PD(MAX)/Amp = (10 • 7.4mA) + (5/2)2/250 = 99mW.

If both channels are loaded identically, the total power

dissipation is 198mW.

At the Absolute Maximum ambient operating temperature,

the junction temperature under these conditions will be:

TJ = TA + (PD • θJA) = 125 + 0.198 • 35 = 132°C

which is less than the absolute maximum junction tem-

perature for the LTC6227.

Refer to the Pin Configuration section for thermal resis-

tances of various packages

Board Layout and Bypass Capacitors

High speed and RF board layout techniques should

be applied due to the very high speeds of the signals

involved. For the LTC6226 SOIC-8 package option, the

feedback should be taken from the FB pin rather than from

the output pin, to reduce signal trace length.

Stray capacitances at the –IN and +IN pins should be

made as low as possible to reduce stability degradation.

Shutdown

The LTC6226 and LTC6227DD have SHDN pins that can

shut down the amplifier to 350µA typical supply current.

The SHDN pin needs to be taken 2.75V below the posi-

tive supply to shut down. When left floating, the SHDN

pin is internally pulled up to 1.2V below the positive sup-

ply and the amplifier remains on. During shutdown, the

output transistors Q15 and Q14 in Figure 1 are in a high

impedance state.

62267 F02

7pF

CPAR

VIN

VOUT

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