LTC6930 datasheet(5/28 Pages) AD

5 / 28 page

LTC6994-1/LTC6994-2

Rev. C

For more information www.analog.com

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC6994C is guaranteed functional over the operating

temperature range of –40°C to 85°C.

Note 3: The LTC6994C is guaranteed to meet specified performance from

0°C to 70°C. The LTC6994C is designed, characterized and expected to

meet specified performance from –40°C to 85°C but it is not tested or

QA sampled at these temperatures. The LTC6994I is guaranteed to meet

specified performance from –40°C to 85°C. The LTC6994H is guaranteed

to meet specified performance from –40°C to 125°C. The LTC6994MP is

guaranteed to meet specified performance from –55°C to 125°C.

Note 4: Delay accuracy is defined as the deviation from the tDELAY

equation, assuming RSET is used to program the delay.

ELECTRICAL CHARACTERISTICS The

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, IN = 0V, DIVCODE = 0 to 15

(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.

Note 5: See Operation section, Table 1 and Figure 2 for a full explanation

of how the DIV pin voltage selects the value of DIVCODE.

Note 6: The IN pin has hysteresis to accommodate slow rising or falling

signals. The threshold voltages are proportional to V+. Typical values can

be estimated at any supply voltage using:

VIN(RISING) ≈ 0.55 • V+ + 185mV and VIN(FALLING) ≈ 0.48 • V+ – 155mV

Note 7: To conform to the Logic IC Standard, current out of a pin is

arbitrarily given a negative value.

Note 8: Output rise and fall times are measured between the 10% and the

90% power supply levels with 5pF output load. These specifications are

based on characterization.

Note 9: Settling time is the amount of time required for the output to settle

within ±1% of the final delay after a 0.5× or 2× change in ISET.

Note 10: Jitter is the ratio of the deviation of the programmed delay to the

mean of the delay. This specification is based on characterization and is

not 100% tested.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Output Rise Time (Note 8)

V+ = 5.5V

V+ = 3.3V

V+ = 2.25V

1.1

1.7

2.7

Output Fall Time (Note 8)

V+ = 5.5V

V+ = 3.3V

V+ = 2.25V

1.0

1.6

2.4

LTC6930 Datasheet(PDF) 5 Page - Analog Devices

LTC6930 Datasheet(HTML) 5 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL