DAC53701 datasheet(21/59 Pages) TI

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8.3.3 DAC Update

The DAC output pin (OUT) is updated at the end of I2C DAC write frame.

8.3.3.1 DAC Update Busy

The DAC_UPDATE_BUSY bit (address D0h) is set to 1 by the device when certain DAC update operations,

such as function generation, transition to margin high or low, or any of the medical alarms are in progress. When

the DAC_UPDATE_BUSY bit is set to 1, do not write to any of the DAC registers. After the DAC update

operation is completed (DAC_UPDATE_BUSY = 0), any of the DAC registers can be written.

8.3.4 Nonvolatile Memory (EEPROM or NVM)

The DACx3701 contain nonvolatile memory (NVM) bits. These memory bits are user programmable and

erasable, and retain the set values in the absence of a power supply. All the register bits, as shown in Table 8-2,

can be stored in the device NVM by setting NVM_PROG = 1 (address D3h). The NVM_BUSY bit (address D0h)

is set to 1 by device when a NVM write or reload operation is ongoing. During this time, the device blocks all

write operations to the device. The NVM_BUSY bit is set to 0 after the write or reload operation is complete; at

this point, all write operations to the device are allowed. The default value for all the registers in the DACx3701 is

loaded from NVM as soon as a POR event is issued. Do not perform a read operation from the DAC register

while NVM_BUSY = 1.

The DACx3701 also implement NVM_RELOAD bit (address D3h). Set this bit to 1 for the device to start an NVM

reload operation. After the operation is complete, the device autoresets this bit to 0. During the NVM_RELOAD

operation, the NVM_BUSY bit is set to 1.

Table 8-2. NVM Programmable Registers

BIT ADDRESS

BIT NAME

D1h

GENERAL_CONFIG

DEVICE_LOCK

11:9

CODE_STEP

8:5

SLEW_RATE

4:3

DAC_PDN

REF_EN

1:0

DAC_SPAN

D2h

CONFIG2

15:14

SLAVE_ADDRESS

13:11

GPI_CONFIG

5:4

INTERBURST_TIME

3:2

PULSE_OFF_TIME

1:0

PULSE_ON_TIME

D3h

TRIGGER

GPI_EN

21h

DAC_DATA

11:2

DAC_DATA

25h

DAC_MARGIN_HIGH

11:4

MARGIN_HIGH (8 most significant bits)

26h

DAC_MARGIN_LOW

11:4

MARGIN_LOW (8 most significant bits)

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DAC53701, DAC43701

SLASEY5 – DECEMBER 2020

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