11 Layout

11.1 Layout Guidelines

Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends

placing a minimum 0.1 µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected

to the CT pin, then minimize parasitic capacitance on this pin so the rest time delay is not adversely affected.

• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a >

0.1 µF ceramic capacitor as near as possible to the VDD pin.

unconnected, make sure to minimize the amount of parasitic capacitance on the pin to < 5 pF.

• Place the pull-up resistors on RESET pin as close to the pin as possible.

11.2 Layout Example

The layout example in shows how the TLV840DL-Q1 is laid out on a printed circuit board (PCB) with a user-

defined delay.

GND

GND

VDD

RESET

CT

MR

VDD

Pull-up resistor required for Open-Drain

(TLV840MADx-Q1) only

Vias used to connect pins for application - specific connections

Figure 11-1. TLV840M-Q1 Recommended Layout

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TLV840-Q1

SNVSBY3 – NOVEMBER 2020

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Product Folder Links: TLV840-Q1