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Low Power CMOS SRAM
256K X 8 Bits
UC62LS2008
-20/-25
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
VCC/0V
1V/ns
0.5VCC
AC TEST LOADS AND WAVEFORMS
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
FIGURE 1A
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
FIGURE 1B
667
Ω
TERMINAL EQUIVALENT
OUTPUT
1.73V
GND
V
CC
1V/ns
1V/ns
10%
90%
90%
10%
ALL INPUT PULSES
FIGURE 2
KEY TO SWITCHING WAVEFORMS
WAVEFORMS
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
DON’T CARE
ANY CHANGE
PERMITTED
CHANGE
STATE
UNKNOWN
DOES NOT
APPLY
CENTER LINE
IS HIGH
IMPEDANCE
OFF STATE
AC ELECTRICAL CHARACTERISTICS (TA=0℃ to 70℃, VCC=3.0V~3.6V)
READ CYCLE
UC62LS2008-20
UC62LS2008-25
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
Min
Typ
Max
Min
Typ
Max
UNIT
tAVAX
tRC
Read Cycle Time
20
-
-
25
-
-
Ns
tAVQV
tAA
Address Access Time
-
-
20
-
-
25
Ns
tELQV
tCE
Chip Select Access Time
-
-
20
-
-
25
Ns
tGLQV
tOE
Output Enable to Output Valid
-
-
10
-
-
10
Ns
tELQX
tCLZ
Chip Select to Output Low Z
5
-
-
5
-
-
Ns
tGLQX
tOLZ
Output Enable to Output Low Z
3
-
-
3
-
-
Ns
tEHQZ
tCHZ
Chip Deselect to Output in High Z
-
-
10
-
-
10
Ns
tGHQZ
tOHZ
Output Disable to Output in High Z
-
-
10
-
-
10
Ns
tAXOX
tOH
Address Chang to Output Change
5
-
-
5
-
-
Ns
U-Chip Technology Corp. LTD.
Preliminary
Rev.1.0
Reserves the right to modify document contents without notice.
PAGE
4
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