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ZMOD4450AI1R Datasheet(PDF) 12 Page - Renesas Technology Corp |
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ZMOD4450AI1R Datasheet(HTML) 12 Page - Renesas Technology Corp |
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12 / 18 page ![]() ZMOD4450 Datasheet © 2019 Integrated Device Technology, Inc. 12 October 30, 2019 11. Test and Calibration As a unique feature, all sampled gas sensor modules are fully tested during IDT’s final test. The final test parameters in Table 8 are applied for each ZMOD4450. All sensor modules are additionally pre-stabilized in the final test; although the user might see a small change in the module’s raw signal during an initial warm-up phase during the first operation. The gas sensor module qualification is based on JEDEC (JESD47) and its subsequent standard (JESD22, JESD78, etc.). Table 8. Final Test Parameters Test Test Object Parameters Test Results Saved in NVM? Electrical ASIC Voltages, current consumption, frequencies, scan pattern No Electrical Module Calibration conditions, tracking ID, resistances Yes Gas Module Sensitivity parameters (slope and intercept) at stimulation with different gas concentrations Yes Gas Module Pre-stabilization No 12. I2C Interface and Data Transmission Protocol The I2C slave device interface supports various bus speeds: Standard Mode (≤100kHz) and Fast Mode (≤ 400kHz). By default, the 7-bit slave address for the serial I2C data interface is set to 32HEX. The implemented data transmission protocol is similar to the one used for conventional EEPROM devices. The register to read/write is selected by a register address pointer. This address pointer must be set during an I2C WRITE operation. After transmission of a register, the address pointer is automatically incremented. An increment from the address FFHEX rolls over to 00HEX. See Figure 5 for an illustration of the data transmission protocol and Figure 5 for a diagram of the bus timing. Table 9 gives the I2C bus characteristics. Recommendation: To validate the READ/WRITE access, write random values to registers 88HEX to 8BHEX and then read these addresses to confirm new values. After this register test, reset the device by disconnecting the power support; otherwise the device might not operate properly. Figure 5. I2C Data Transmission Protocol Write Read Write From master to slave From slave to master S START condition P STOP condition A N Acknowledge Not acknowledge WRITE Access RAM READ Access NVM and RAM 0 S Slave Addr 7 Bit 1 A Address 8 Bit N P Data 8 Bit A S Slave Addr 7 Bit A A Data 8 Bit A Data 8 Bit ... 0 S Slave Addr 7 Bit A Address P Data 8 Bit A A Data 8 Bit A Data 8 Bit ... A |
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