TPS2340A

SLUS528A – MARCH 2002 – REVISED AUGUST 2002

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APPLICATION INFORMATION

Similar to input data, serial output data has been ordered to facilitate cascading TPS2340A devices. Assuming

a six-slot implementation, as input data arrives in the order of slot A first, followed by data for slots B through

F, output data is delivered in reverse order, slot F data first, then data for slots E through A. For a PCI hot-plug

controller that supports 6 slots, 48 bits (8 per slot) are shifted out by the controller any time a slot control state

needs to be changed. At the conclusion of a shift-out process, output data for slots A and B is contained in the

device (electrically) closest to the PCI hot-plug controller. Output data for each slot is delivered in the bit order

described in Table 10.

Table 10. Operational Mode Output Data Bit Order

BIT

NUMBER

FUNCTION

0

Slot F Pwren state (1 = turn on power)

1

Slot F CLKEN state (1 = enable the clock)

2

Slot F BUSEN state (1 = enable the bus)

3

Slot F PCIRST state (0 = assert PCIRST)

4

Slot F PWRLED state (1 = turn on power LED)

5

Slot F ATTLED state (1 = turn on attention LED)

6

Reserved

7

Reserved

8

Slot E Pwren state

9

Slot E CLKEN state

10

Slot E BUSEN state

11

Slot E PCIRST state

12

Slot E PWRLED state

13

Slot E ATTLED state

14

Reserved

15

Reserved

16

…47

SODO pin data for slots D, C, B and A follows

The output data for the six slots is shifted out using the SOC clock. After the appropriate data pattern is

established in the shift registers, this data is parallel clocked into registers via latch clocks. These registers drive

the output pins and controls. The SOLC pin serves as the latch clock for the Pwrenx, BUSENx, CLKENx,

PWRLEDx, and ATTLEDx outputs.

The SORLC pin serves as the latch clock for the RESETx pins. Two latch clocks are used so that the PCI bus

timing requirements between REQ64, TRDY, DEVSEL, and STOP and the slot’s RST signal can be more easily

controlled by the hot-plug controller.

If a fault occurs, as indicated by the assertion of the Faultx signal (where Faultx = Pwrfltx and Auxfltx), the

RESETx pin asynchronously asserts and the CLKENx and BUSENx pins are asynchronously deasserted.