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F1240 Datasheet(PDF) 1 Page - Renesas Technology Corp |
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F1240 Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 35 page  Dual Channel IF Digital Variable Gain Amplifier 10MHz to 500MHz F1240 Datasheet © 2018 Integrated Device Technology, Inc. 1 September 11, 2018 Description The F1240 is a dual channel IF variable gain amplifier for diversity basestation receivers. Each channel has 31.5dB of total attenuation and a 0.5dB attenuation step. The device offers significantly better noise and distortion performance than currently available devices. It is packaged in a compact 5mm x 5mm QFN with 200Ω differential input and output impedances for ease of integration into the receiver lineup. Competitive Advantage The F1240 IF VGA improves system signal-to-noise (SNR), especially at lower gain settings. With IDT’s proprietary FlatNoiseTM technology both OIP3 and noise figure are kept virtually flat while gain is backed off, enhancing SNR significantly under high level interferer conditions, and greatly benefiting 2G/3G/4G Multi-Carrier IF sampling receivers. The fast settling time, less than 15ns, gain step of 0.5dB coupled with the excellent differential linearity allow for signal to noise ratio (SNR) to be maximized further by targeting the minimum necessary gain in small, accurate increments. The matched output does not require a terminating resistor, thus the gain and distortion performance are preserved when driving bandpass anti-alias filters. See the Applications Information section for more details and benefits of the F1240 in IF sampling receivers. Typical Applications Base Station 2G, 3G, 4G, TDD radio cards Repeaters and E911 systems Digital Pre-Distortion Point to Point Infrastructure Public Safety Infrastructure Features Ideal for systems with high SNR requirements 20dB typical Maximum Gain 31.5dB gain control range 6 bit control via serial or parallel control 0.5dB Gain Steps Excellent Noise Figure : 4.0dB NF degrades just 1.3dB @ 10dB below Max Gain 200Ω Differential Matched Input 200Ω Differential Matched Output No termination resistors required 10MHz – 500MHz frequency range Ultra-Linear: OIP3 +47dBm typical Excellent 2nd Harmonic Rejection External current setting resistors Very fast settling < 15ns Individual Power Down Modes Extremely Low Power: 80mA / Chan 5 × 5 32-QFN package Block Diagram Figure 1. Block Diagram Bias Control ISET [2] VCC Logic Decoder STBY_B OUT_B+ OUT_B- OUT_A+ OUT_A- IN_B+ IN_B- IN_A+ IN_A- VMODE STBY_A CLK DATA CSb Parallel [12] FlatNoiseTM |
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