ISO6740FDWR datasheet(21/44 Pages) TI

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6.20 Switching Characteristics—1.8-V Supply

VCC1 = VCC2 = 1.8 V ±5% (over recommended operating conditions unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

tPLH, tPHL

Propagation delay time

@100kbps

See Figure 7-1

PWD

Pulse width distortion(1) |tPHL – tPLH|

0.7

8.2

tsk(o)

Channel-to-channel output skew time(2)

Same-direction channels

tsk(pp)

Part-to-part skew time(3)

8.8

Output signal rise time

See Figure 7-1

2.7

5.3

Output signal fall time

2.7

5.3

tPHZ

Disable propagation delay, high-to-high impedance

output

See Figure 7-2

40.3

tPLZ

Disable propagation delay, low-to-high impedance

output

40.3

tPZH

Enable propagation delay, high impedance-to-high

output for ISO674x

51.4

tPZL

Enable propagation delay, high impedance-to-low

output for ISO674x

51.4

tPU

Time from UVLO to valid output data

300

tDO

Default output delay time from input power loss

Measured from the time VCC goes

below 1.2V. See Figure 7-3

0.1

0.3

tie

Time interval error

216 – 1 PRBS data at 50 Mbps

(1)

Also known as pulse skew.

(2)

tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same

direction while driving identical loads.

(3)

tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads.

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ISO6740, ISO6741, ISO6742

SLLSFJ6C – DECEMBER 2019 – REVISED JANUARY 2021

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