LTC4449 datasheet(8/18 Pages) AD

8 / 18 page

LTC7060

Rev. A

For more information www.analog.com

TIMING DIAGRAM

PWM

90%

10%

r(TG)

PLH(TG)

10%

90%

f(BG)

PHL(BG)

VIL(BG)

VENF

90%

tPL(EN)

10%

tPH(EN)

ENR

tr(BG)

tPLH(BG)

tf(TG)

PHL(TG)

VIL(BG)

VIL(TG)

PHL(BG)

7060 TD

TG HIGH

VIH(TG)

VIL(BG)

VIL(TG)

VIH(BG)

PWM

TG LOW

BG LOW

BG HIGH

7060 F01

BG LOW

BG HIGH

Figure 1. Three-State PWM Operation

OPERATION

OVERVIEW

The LTC7060 receives a ground-referenced, low volt-

age digital PWM signal to drive two N-channel power

MOSFETs in a half-bridge configuration. The gate of the

low side MOSFET is driven high or low, swinging between

BGVCC and BGRTN, depending on the state of the PWM

pin. Similarly, the gate of the high side MOSFET is driven

complimentary to the low side MOSFET, swinging between

BST and SW.

Both the low side and high side drivers are floating gate

drivers. The unique double floating architecture makes the

gate driver outputs robust and less sensitive to ground

noise. The symmetric design allows the half-bridge output

to be inverting or non-inverting of the input logic.

VCC SUPPLY

VCC is the power supply for the LTC7060’s internal circuitry.

An internal 4.5V supply is generated from the VCC supply

to bias most of the internal circuits referred to SGND. The

VCC pin may be tied to the BGVCC pin if SGND and BGRTN

are at the same potential. VCC is independent of VIN.

INPUT STAGE (PWM, EN)

The LTC7060 employs a three-state PWM input with

fixed transition thresholds. The relationship between

the transition thresholds and three input states of the

LTC7060 is illustrated in Figure 1. When the voltage on

PWM is greater than the threshold VIH(TG), TG is pulled up

to BST, turning the high side MOSFET on. This MOSFET

will stay on until PWM falls below VIL(TG). Similarly, when

PWM is less than VIH(BG), BG is pulled up to BGVCC, turn-

ing the low side MOSFET on. BG will stay high until PWM

increases above the threshold VIL(BG).

The hysteresis between the corresponding VIH and VIL

voltage levels eliminates false triggering due to the noise

during switch transitions. However, care should be taken

to keep noise from coupling into the PWM pin, particularly

in high frequency, high voltage applications.

The thresholds are positioned to allow for a region in

which both BG and TG are low. An internal resistor divider

LTC4449 Datasheet(PDF) 8 Page - Analog Devices

LTC4449 Datasheet(HTML) 8 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Datasheet Download

Link URL