LTC4449 datasheet(10/18 Pages) AD

10 / 18 page

LTC7060

Rev. A

For more information www.analog.com

OPERATION

The LTC7060 contains both undervoltage and overvoltage

lockout detectors that monitor the VCC supply. When VCC

falls below 5.3V or rises above 14.6V, BG and TG pins are

pulled to BGRTN and SW, respectively, turning off both

the external MOSFETs. When VCC has adequate supply

voltage but less than the overvoltage threshold, normal

operation will resume.

Additional undervoltage lockout circuitry is included in

each floating driver supply. The BG will be pulled down to

BGRTN when the floating voltage from BGVCC to BGRTN

falls below 3.3V. Similarly, the TG will be pulled down

to SW when the floating voltage from BST to SW is less

than 3.3V.

The normal operation and undervoltage/overvoltage logic

table is shown in Table 1.

Table 1. Normal Operation and Undervoltage/Overvoltage Logic

PWM

VCC

UVLO or

OVLO

(BST-SW)

UVLO

(BGVCC-

BGRTN)

UVLO

HIGH-Z

Note: “X” means "Don't Care"

ADAPTIVE SHOOT-THROUGH PROTECTION

Internal adaptive shoot-through protection circuitry moni-

tors the external MOSFETs to ensure that they do not

conduct simultaneously. The LTC7060 does not allow the

bottom MOSFET to turn on until the gate-source voltage

on the top MOSFET is sufficiently low, and vice-versa. This

feature improves efficiency and reliability by eliminating

potential shoot-through current through the MOSFETs

during switching transitions.

PROGRAMMABLE DEAD-TIME

To ensure robust shoot-through protection in high voltage

half-bridge configuration and switched capacitor converter

applications, the LTC7060 provides a DT pin which can

be used to program the propagation delay during BG/TG

low to TG/BG high transition (Dead-Time). An external

resistor (RDT) from the DT pin to the SGND equally sets

both the BG low to TG high propagation delay and the TG

low to BG high propagation delay. Their relationship can

be seen in Figure 3. The Dead-Time can be estimated by

the following equation when the RDT is less than 100kΩ:

Dead-Time = RDT • 0.44ns/kΩ + 32ns

If the DT pin is shorted to SGND, the Dead-Time is 32ns.

If the DT Pin is floating, the Dead-Time is around 250ns.

RDT (kΩ)

100

7060 F03

Figure 3. Dead-Time vs RDT

FAULT FLAG

The FLT pin is connected to the open-drain of an internal

N-channel MOSFET. It needs a pull-up resistor (e.g. 51k)

tied to a supply such as VCC or any other bias voltage up

to 15V. The FLT pin is pulled low to SGND immediately if

any of these conditions are met:

a. The VCC is below its UVLO threshold or above its

OVLO threshold.

b. (BGVCC-BGRTN) is below its UVLO threshold.

c. (BST-SW) is below its UVLO threshold.

d. The junction temperature reaches approximately

180°C.

When all the faults are cleared, the FLT pin is pulled up by

the external resistor after a built-in 100µs delay.

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