LTM8083 datasheet(7/24 Pages) AD

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LTM8083

Rev. 0

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PIN FUNCTIONS

GND (Bank 0, Pin D7): Tie these GND pins to a local

ground plane below the LTM8083 and the circuit com-

ponents. In most applications, the majority of the heat

of the LTM8083 flows out through these pads, so the

printed circuit design has a large impact on the thermal

performance of the part. See the PCB Layout and Thermal

Considerations sections for more details. Return the feed-

back divider (RFB) to this net.

VIN (Bank 1): Input Power. The VIN pin supplies current

to the internal power switches. This pin must be locally

bypassed with an external, low ESR ceramic capacitor.

VOUT (Bank 2): Power Output Pins. Apply the output filter

capacitor and the output load between these pins and

GND pins.

SVIN (Pin A6): Bias Supply. The SVIN pin supplies the

internal circuitry and the INTVCC linear regulator. Connect

this pin to VIN or another power supply. Bypass this pin

to ground with a ceramic capacitor.

TST2 (Pin A7): Test Pin 2. This pin is used in production

testing. Do not drive a voltage into this pin; This pin must

be tied to GND.

EN/UVLO (Pin B6): Enable and Undervoltage Lockout.

Force the pin below 0.3V to shut down the part and reduce

VIN quiescent current to 0.9μA. Force the pin above

1.240V for normal operation. The accurate 1.210V falling

threshold can be used to program an undervoltage lock-

out (UVLO) threshold with a resistor divider from VIN to

ground. An accurate 2.5μA pull-down current allows the

programming of VIN UVLO hysteresis. If neither function

is used, tie this pin directly to VIN.

OVLO (Pin B7): Overvoltage Lockout. The OVLO pin is

used to program an overvoltage lockout (OVLO) threshold

with a resistor divider from VIN to ground. Force the pin

above 1.250V to pull SS pin to ground and stop switching.

If not used, tie this pin to ground.

INTVCC (Pin C6): Internal 3.6V Linear Regulator Output.

Powered from the SVIN pin, the INTVCC supplies the

internal control circuitry and gate drivers. No decoupling

ceramic capacitor is required.

CTRL (Pin C7): ISP-ISN Current Sense Adjustment. The

voltage on this pin determines current limit threshold

voltage of ISP-ISN. The current limit threshold is 100mV

when this pin is floated. Apply a voltage below 1.35V to

reduce the current limit threshold of ISP-ISN across the

output sense resistor. This pin is internally pulled up to 2V

reference voltage with a 100k resistor. See the Applications

Information section for more details.

ISMON (Pin D6): ISP-ISN Current Monitor. This pin pro-

duces a voltage that is 10 times the voltage of VISP-VISN

plus 0.25V offset voltage. ISMON will equal 1.25V when

VISP – VISN = 100mV.

VC (Pin E6): Error Amplifier Output. The VC pin is nor-

mally left open in LTM8083 applications as it is already

internally compensated.

RT (Pin E7): Switching Frequency Setting. Connect a

resistor from this pin to ground to set the internal oscil-

lator frequency from 300kHz to 2MHz. See Table 1 for

resistor values to set common switching frequencies.

ISN (Pin F3): Negative Terminal of Current Sense Resistor.

Ensure accurate current sense with Kelvin connection.

SS (Pin F6): Soft-Start. A 10nF capacitor has been inte-

grated inside LTM8083 for start-up. To increase the

built-in soft-start time, connect a capacitor from SS to

GND. If no additional soft-start time is required, leave

this pin floating.

FB (Pin F7): Feedback. The LTM8083 regulates its FB

pin to 1V. Connect a resistor divider from this pin to the

output and to ground to set the output voltage. When an

output current sense resistor is connected to ISP and

ISN, connect the resistor network to ISN for improved

load regulation.

PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE

LAYOUT CAREFULLY.

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