LTM8083 datasheet(19/24 Pages) AD

19 / 24 page

LTM8083

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

PC Board Layout Checklist/Examples

The high integration of LTM8083 makes the PCB board

layout very simple and easy. However, to optimize its

electrical and thermal performance, some layout consid-

erations are still necessary.

• Use large PCB copper areas for high current paths,

including VIN, GND and VOUT. It helps to minimize the

PCB conduction loss and thermal stress.

• Place high frequency ceramic input and output capac-

itors next to the VIN, GND and VOUT pins to minimize

high frequency noise.

• Place a dedicated power ground layer underneath

the unit.

• Use planes for VIN and VOUT to maintain good voltage

filtering and to keep power losses low.

• To minimize the via conduction loss and reduce module

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

• Do not put via directly on the pad, unless they are

capped or plated over.

• The ground plane layer should not have any traces.

• Flood all unused areas on all layers with copper.

Flooding with copper will reduce the temperature rise

of module. Connect the copper areas to GND

• Keep separation between SYNC and RT pin traces to

minimize noise due to crosstalk between these signals.

• Route ISP and ISN traces together with minimum PCB

trace spacing. Avoid sense lines passing through noisy

areas, such as switch nodes. Ensure accurate current

sensing with Kelvin connections at the current sense

resistor.

• Connect the optional VC pin compensation capacitor

close to the module, between VC and the signal ground.

The capacitor helps to filter the effects of PCB noise

and output voltage ripple voltage from the compensa-

tion loop.

Figure 22 gives a good example of the recommended

layout.

Table 6. Output Voltage Response vs Component Matrix (Refer to Figure 23)

COUT

PART NUMBER

VALUE

MURATA

GCM32EC71H106KA03

10µF, 50V, 1210, X7S

VIN

(V)

VOUT

(V)

fSW (MHz)

COUT

(CER CAP)

COMPENSATION

LOAD STEP (A)

LOAD STEP RISING

AND FALLING TIME

(µs)

PK-PK

DEVIATION

(mV)

RECOVERY

TIME

(μs)

3.3

1, See Note

10µF

Internal

0 – 0.375

640

150

10µF

Internal

0 – 0.375

280

10µF

Internal

0 – 0.375

150

100

10µF

Internal

0 – 0.375

320

150

10µF

Internal

0 – 0.375

440

170

10µF

Internal

0 – 0.375

440

230

10µF

Internal

0 – 0.375

350

200

10µF

Internal

0 – 0.375

340

200

10µF

Internal

0 – 0.375

1600

200

10µF

Internal

0 – 0.375

2000

220

Note: Use 40.2kΩ RT resistor to set switching frequency at 1MHz.

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