DFDF2812ZHHAR datasheet(3/175 Pages) TI

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4 Functional Block Diagram

INT[12:1]

CLKIN

Real-Time JTAG

Peripheral Bus

C28x CPU

INT14

NMI

INT13

Memory Bus

eCAN

SCIA/SCIB

12-Bit ADC

External Interrupt

Control

(XINT1/2/13, XNMI)

EVA/EVB

Memory Bus

McBSP

System Control

(Oscillator and PLL

Peripheral Clocking

Low-Power Modes

Watchdog)

FIFO

PIE

(96 Interrupts)

(A)

SPI

FIFO

TINT0

TINT1

TINT2

CPU-Timer 0

CPU-Timer 1

CPU-Timer 2

16 Channels

GPIO Pins

XRS

X1/XCLKIN

XF_XPLLDIS

Protected by the code-security module.

XINT13

XNMI

OTP

1K x 16

H0 SARAM

8K x 16

Boot ROM

4K x 16

Flash

128K x 16 (F2812)

128K x 16 (F2811)

64K x 16 (F2810)

Control

Address (19)

Data (16)

External

Interface

(XINTF)

(B)

L0 SARAM

4K x 16

L1 SARAM

4K x 16

M1 SARAM

1K x 16

M0 SARAM

1K x 16

A. 45 of the possible 96 interrupts are used on the devices.

B. XINTF is available on the F2812 device only.

Figure 4-1. Functional Block Diagram

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TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1

TMS320F2812, TMS320F2812-Q1

SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021

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TMS320F2812-Q1

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