DFDF2812ZHHAR datasheet(73/175 Pages) TI

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8.12.5.15.7 Sequential Sampling Mode (Single-Channel) (SMODE = 0)

In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax to Bx).

The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software trigger, or from

an external ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the selected channel on

every Sample/Hold pulse. The conversion time and latency of the Result register update are explained below.

The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. The selected

channels will be sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulse width can be

programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).

Analog Input on

Channel Ax or Bx

ADC Clock

Sample and Hold

SH Pulse

SMODE Bit

dschx_n

dschx_n+1

Sample n

Sample n+1

Sample n+2

ADC Event Trigger from EV

or Other Sources

d(SH)

Figure 8-37. Sequential Sampling Mode (Single-Channel) Timing

8.12.5.15.7.1 Sequential Sampling Mode Timing

SAMPLE n

SAMPLE n + 1

AT 25-MHz

ADC CLOCK,

tc(ADCCLK) = 40 ns

REMARKS

td(SH)

Delay time from event

trigger to sampling

2.5tc(ADCCLK)

tSH

Sample/

Hold width/

Acquisition width

(1 + Acqps) * tc(ADCCLK)

40 ns with Acqps = 0

Acqps value = 0–15

ADCTRL1[8:11]

td(schx_n)

Delay time for first

result to appear in the

Result register

4tc(ADCCLK)

160 ns

td(schx_n+1)

Delay time for

successive results to

appear in the Result

(2 + Acqps) * tc(ADCCLK)

80 ns

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TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1

TMS320F2812, TMS320F2812-Q1

SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021

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