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ADRV9010BBCZ Datasheet(PDF) 21 Page - Analog Devices |
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ADRV9010BBCZ Datasheet(HTML) 21 Page - Analog Devices |
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21 / 115 page  Data Sheet ADRV9010 Rev. E | Page 21 of 115 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VSSA SERD OUTH+ SERD OUTD+ VSSA TX4+ TX4– VSSA GPIO_ ANA_5 VSSA RX4+ RX4– VSSA AUXADC _2 AUXADC _3 VSSA RX3+ RX3– U T R P N M L K J H G F E D C B A VSSA VSSA TX3+ TX3– VSSA VTXLO_ IP3 VSSA VRXLO_ IP3 VSSA VSSA VSSA TX2+ TX2– VSSA VSSA VSSA VSSA VSSA VANA3_ 1P8 VSSA VSSA VSSA VSSA VSSA VSSA VAUXVCO _1P0 VSSA VSSA VSSA VSSA RX2+ VSSA GPIO_ ANA_7 GPIO_ ANA_6 VAUXSYN _1P3 VSSA DEVCLK+ DEVCLK– VSSA VAUXVCO _1P3 GPIO_ ANA_1 GPIO_ ANA_0 VSSA RBIAS VSSA RX2– VSSA VANA2_ 1P3 VSSA VSSA VSSA VSSA SYSREF+ SYSREF– VSSA VSSA VSSA VSSA VSSA VANA1_ 1P3 VSSA VSSA EXT_ LO2– VSSA ORX3+ ORX3– VSSA TX3_EN GPIO_11 GPIO_9 GPIO_3 TX2_EN VSSA ORX1+ ORX1– VSSA EXT_ LO1+ AUXADC _1 EXT_ LO2+ VSSA VSSA VSSA VSSA ORX_ CTRL_C GPIO_12 GPIO_10 GPIO_4 ORX_ CTRL_B VSSA VSSA VSSA VSSA EXT_ LO1– AUXADC _0 VSSA VRFVCO2 _1P3 VSSA VRFVCO2 _1P0 VSSA RX3_EN GPIO_13 VDIG_1P0 GPIO_5 RX2_EN VSSA VRFVCO1 _1P0 VSSA VRFVCO1 _1P3 VSSA VSSA VSSA VCONV2 _1P8 VSSA VSSA VSSA GPIO_17 GPIO_14 VSSD GPIO_6 GPIO_0 VSSA VSSA VSSA VCONV1 _1P8 VSSA RX1+ VSSA VCONV2 _1P3 VSSA VRFSYN2 _1P3 VSSA RX4_EN GPIO_15 VDIG_1P0 GPIO_7 RX1_EN VSSA VRFSYN1 _1P3 VSSA VCONV1 _1P3 VSSA RX1– VSSA VCONV2 _1P0 VSSA VSSA VSSA GPIO_18 GPIO_16 VSSD GPIO_8 GPIO_1 VSSA VSSA VSSA VCONV1 _1P0 VSSA VSSA GPIO_ ANA_4 VSSA ORX4+ ORX4– VSSA ORX_ CTRL_D SPI_DIO VDIG_1P0 SPI_EN ORX_ CTRL_A VSSA ORX2+ ORX2– VSSA GPIO_ ANA_2 GPIO_ ANA_3 VSSA VSSA VSSA VSSA VSSA TX4_EN SPI_DO VSSD SPI_CLK TX1_EN VSSA VSSA VSSA VSSA VSSA VSSA VANA4 _1P8 VSSA VSSA VCLKVCO _1P3 SYNCIN3+ GPINT2 GPINT1 GPIO_2 SYNCIN1+ SYNCIN1– SYNC OUT2+ SYNC OUT2– VANA1 _1P8 TX1+ VSSA VSSA VSSA VCLKVCO _1P0 SYNCIN3– SYNCIN2+ SYNCIN2– VSSA TEST_EN VJVCO _1P8 SYNC OUT1+ VSSA TX1– VSSA VSSA VSSA VCLKSYN _1P3 VSSA VJSYN _1P0 VSSA NIC VSSA VSSA VSSA SYNC OUT1– VSSA VSSA SERD OUTD– SERD OUTC+ SERD OUTC– SERD OUTB+ SERD OUTB– SERD OUTA+ SERD OUTA– VSSA SERD IND– SERD IND+ SERD INC+ SERD INC– SERD INB– SERD INB+ SERD INA+ SERD INA– SERD OUTH– SERD OUTG+ SERD OUTG– SERD OUTF+ ANALOG GROUND DIGITAL GROUND ANALOG POWER DIGITAL POWER ANALOG INPUTS/OUTPUTS DIGITAL INPUTS/OUTPUTS ANALOG GPIO AUXILIARY ADC INPUTS SPI BUS LVDS SERDES CONTROLS SERDES INPUTS/OUTPUTS DIFFERENTIAL SYSREF SIGNAL NOT INTERNALLY CONNECTED SERD OUTF– SERD OUTE+ SERD OUTE– VSSA SERD INH– SERD INH+ SERD ING+ SERD ING– SERD INF– SERD INF+ SERD INE+ SERD INE– 1234 56789 ADRV9010 TOP VIEW (Not to Scale) 10 11 12 13 14 15 16 17 RESET NIC VANA2_ 1P8 VDES _1P0 VDES _1P0 VTT_DES VSER _1P0 VSER _1P0 VIF Figure 2. Pin Configuration |
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