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MAX32010 Datasheet(PDF) 21 Page - Maxim Integrated Products |
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MAX32010 Datasheet(HTML) 21 Page - Maxim Integrated Products |
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21 / 31 page ![]() MAX32010 25V Span, 1.2A Device Power Supply (DPS) www.maximintegrated.com Maxim Integrated | 21 Configuration and Control Configuration of the MAX32010 is achieved through the serial interface, and through the dedicated logic-control inputs , , and IDDQSEL. The serial interface has a shift register, an input register, and a DPS register (Figure 2). Serial data does not directly affect the DPS until the data reaches the DPS register. Control of data flow to the DPS register is through two control bits (A0 and C0) and the logic input ( . asynchronously transfers data from the input register into the DPS register. If is held low when data is latched into the input register, then the data transfers directly (transparently) into the DPS register. This allows changing the state of the DPS coincident with the end of serial-port data communication, or asynchronously with respect to serial-port communications. Asynchronous update using facilitates simultaneous updates of multiple daisy-chained DPS devices. DPS Data Control Bits An 18-bit word programs the MAX32010. Table 1 outlines the 18-bit control word structure. Serial Interface Data Flow Control Bits Bits 0 and 1 (C0 and A0) specify if and how data transfers from the shift register to the input and DPS registers. The specified actions shown in Table 2 occur when CS goes high (Figures 3 and 4). INPUT REGISTERS CONTROL DECODE SHIFT REGISTER 2 16 CS SCLK DIN DOUT DPS REGISTER D17 D16 D1 D0 LOAD Figure 2. Serial Interface When A0 = C0 = 0 (NOP), data moves through the shift register to DOUT without a change in mode or operation. This is useful when daisy-chaining devices to shift operational data through a number of devices to a specific device without altering some or all the device’s operational data. To update multiple daisy-chained devices simultaneously, use A0 = 1 and C0 = 0 to load the input register of the devices to be updated and activate after goes high (Figure 4). If is held low while is raised, data latched to the input register is also latched to the DPS register, independent of the state of C0. |
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