Z8F2402 datasheet(13/246 Pages) ZILOG

13 / 246 page

PS017610-0404

List of Tables

Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x

Z8 Encore!®

Table 32.

IRQ2 Enable and Priority Encoding . . . . . . . . . . . . . . . . . 53

Table 33.

IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . 53

Table 34.

IRQ2 Enable Low Bit Register (IRQ2ENL) . . . . . . . . . . . 54

Table 35.

IRQ2 Enable High Bit Register (IRQ2ENH) . . . . . . . . . . 54

Table 36.

Interrupt Edge Select Register (IRQES) . . . . . . . . . . . . . . 55

Table 37.

Interrupt Port Select Register (IRQPS) . . . . . . . . . . . . . . . 55

Table 38.

Interrupt Control Register (IRQCTL) . . . . . . . . . . . . . . . . 56

Table 39.

Timer 0-3 High Byte Register (TxH) . . . . . . . . . . . . . . . . 67

Table 40.

Timer 0-3 Low Byte Register (TxL) . . . . . . . . . . . . . . . . . 67

Table 41.

Timer 0-3 Reload High Byte Register (TxRH) . . . . . . . . . 68

Table 42.

Timer 0-3 Reload Low Byte Register (TxRL) . . . . . . . . . . 68

Table 43.

Timer 0-3 PWM High Byte Register (TxPWMH) . . . . . . 69

Table 44.

Timer 0-3 PWM Low Byte Register (TxPWML) . . . . . . . 69

Table 45.

Timer 0-3 Control Register (TxCTL) . . . . . . . . . . . . . . . . 70

Table 46.

Watch-Dog Timer Approximate Time-Out Delays . . . . . . 73

Table 47.

Watch-Dog Timer Control Register (WDTCTL) . . . . . . . 75

Table 48.

Watch-Dog Timer Reload Upper Byte Register (WDTU) 76

Table 49.

Watch-Dog Timer Reload High Byte Register (WDTH) . 76

Table 50.

Watch-Dog Timer Reload Low Byte Register (WDTL) . . 77

Table 51.

UARTx Transmit Data Register (UxTXD) . . . . . . . . . . . . 86

Table 52.

UARTx Receive Data Register (UxRXD) . . . . . . . . . . . . . 87

Table 53.

UARTx Status 0 Register (UxSTAT0) . . . . . . . . . . . . . . . 87

Table 54.

UARTx Control 0 Register (UxCTL0) . . . . . . . . . . . . . . . 89

Table 55.

UARTx Status 1 Register (UxSTAT1) . . . . . . . . . . . . . . . 89

Table 56.

UARTx Control 1 Register (UxCTL1) . . . . . . . . . . . . . . . 90

Table 57.

UARTx Baud Rate High Byte Register (UxBRH) . . . . . . 91

Table 58.

UARTx Baud Rate Low Byte Register (UxBRL) . . . . . . . 92

Table 59.

UART Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 60.

SPI Clock Phase (PHASE) and Clock Polarity

(CLKPOL) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 61.

SPI Data Register (SPIDATA) . . . . . . . . . . . . . . . . . . . . 106

Table 62.

SPI Control Register (SPICTL) . . . . . . . . . . . . . . . . . . . . 107

Table 63.

SPI Status Register (SPISTAT) . . . . . . . . . . . . . . . . . . . . 108

Table 64.

SPI Mode Register (SPIMODE) . . . . . . . . . . . . . . . . . . . 109

Table 65.

SPI Baud Rate High Byte Register (SPIBRH) . . . . . . . . 110

Table 66.

SPI Baud Rate Low Byte Register (SPIBRL) . . . . . . . . . 110

Z8F2402 Datasheet(PDF) 13 Page - Zilog, Inc.

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