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Z8F2402 Datasheet(PDF) 39 Page - Zilog, Inc. |
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Z8F2402 Datasheet(HTML) 39 Page - Zilog, Inc. |
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39 / 246 page ![]() PS017610-0404 Register File Address Map Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x Z8 Encore!® 21 Timer 3 (not available in 40- and 44- Pin Packages) F18 Timer 3 High Byte T3H 00 66 F19 Timer 3 Low Byte T3L 01 66 F1A Timer 3 Reload High Byte T3RH FF 67 F1B Timer 3 Reload Low Byte T3RL FF 67 F1C Timer 3 PWM High Byte T3PWMH 00 69 F1D Timer 3 PWM Low Byte T3PWML 00 69 F1E Reserved — XX F1F Timer 3 Control T3CTL 00 70 F20-F3F Reserved — XX UART 0 F40 UART0 Transmit Data U0TXD XX 86 UART0 Receive Data U0RXD XX 87 F41 UART0 Status 0 U0STAT0 0000011Xb 87 F42 UART0 Control 0 U0CTL0 00 89 F43 UART0 Control 1 U0CTL1 00 89 F44 UART0 Status 1 U0STAT1 00 87 F45 Reserved — XX F46 UART0 Baud Rate High Byte U0BRH FF 91 F47 UART0 Baud Rate Low Byte U0BRL FF 91 UART 1 F48 UART1 Transmit Data U1TXD XX 86 UART1 Receive Data U1RXD XX 87 F49 UART1 Status 0 U1STAT0 0000011Xb 87 F4A UART1 Control 0 U1CTL0 00 89 F4B UART1 Control 1 U1CTL1 00 89 F4C UART1 Status 1 U1STAT1 00 87 F4D Reserved — XX F4E UART1 Baud Rate High Byte U1BRH FF 91 F4F UART1 Baud Rate Low Byte U1BRL FF 91 I 2C F50 I 2C Data I2CDATA 00 118 F51 I 2C Status I2CSTAT 80 118 F52 I 2C Control I2CCTL 00 119 F53 I 2C Baud Rate High Byte I2CBRH FF 121 F54 I 2C Baud Rate Low Byte I2CBRL FF 121 F55-F5F Reserved — XX Serial Peripheral Interface (SPI) F60 SPI Data SPIDATA XX 106 F61 SPI Control SPICTL 00 107 Table 6. Register File Address Map (Continued) Address (Hex) Register Description Mnemonic Reset (Hex) Page # XX=Undefined |
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