IMXRT1024IEC datasheet(9/90 Pages) NXP

9 / 90 page

Architectural overview

i.MX RT1024 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 11/2020

NXP Semiconductors

Architectural overview

The following subsections provide an architectural overview of the i.MX RT1024 processor system.

2.1

Block diagram

Figure 3 shows the functional modules in the i.MX RT1024 processor system1.

Figure 3. i.MX RT1024 system block diagram

1. Some modules shown in this block diagram are not offered on all derivatives. See Table 2 for details.

Arm® Cortex®-M7

Security

Secure JTAG

PLL, OSC

FPU

Analog

eDMA

Up to 256 KB TCM

16 KB D-cache

Connectivity

8 x UART

4 x Watchdog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel QSPI FLASH

with Bus Encryption Engine

S/PDIF Tx/Rx

USB 2.0 OTG

w/ PHY

4 x SPI

5 x 5 Keypad

MPU

Internal Memory

96 KB ROM

4 x Analog Comparator

DCDC and LDO

2 x Quadrature ENC

External Memory Controller

8/16-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control

Main CPU Platform

Core

IOMUX

Ciphers and RNG

Secure RTC

eFuse

HAB

256 KB SRAM/TCM

Timers

4 MB Flash

2 x eMMC 4.5/SD 3.0

4 x I2C

3 x I2S

GPIO

10/100 ENET

with IEEE® 1588

2 x CAN

2 x FlexPWM

2 x GP Timer

2 x QuadTimer

2 x ADC

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